Re: [patch] MIPS64 R4k TLB refill CP0 hazards
From: Maciej W. Rozycki <hidden>
Date: 2002-07-31 11:32:23
Possibly related (same subject, not in this thread)
- 2002-08-02 · Re: [patch] MIPS64 R4k TLB refill CP0 hazards · Carsten Langgaard <hidden>
- 2002-08-02 · Re: [patch] MIPS64 R4k TLB refill CP0 hazards · Ralf Baechle <hidden>
- 2002-08-02 · Re: [patch] MIPS64 R4k TLB refill CP0 hazards · Carsten Langgaard <hidden>
- 2002-08-01 · Re: [patch] MIPS64 R4k TLB refill CP0 hazards · Ralf Baechle <hidden>
- 2002-08-01 · Re: [patch] MIPS64 R4k TLB refill CP0 hazards · Maciej W. Rozycki <hidden>
On Wed, 31 Jul 2002, Ralf Baechle wrote:
Nope, on R4000 four cycles are needed between the tlbwr and a eret instruction; on the R4600 just two.
Ugh, I missed this entirely, thanks for pointing it out. The doc implies three cycles for the R4000 actually, though. -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +