Huh? Unless something major has changed since the last time I looked at
DMA hardware (and it has been a few years), DMA uses the same transfer
sequence from the devices point of view as PIO.  The fact that the 
transfer is under the control of another device rather than a program 
should be transparent to the target device.  Impedance mismatches,
reflections and constructive and destructive interference caused by
cable problems don't care about who's in control of the busses.

I can see a possible problem with cache consistency causing problems
with PIO, but there are similar (abet in some sense inverted or
reversed) problems with DMA.

Actually, it's not the same transfer sequence (and it's not the same
ATA commands neither). Look for an ATA spec and check out the signals
on the wire, DMA is different at the device level as well.

In addition, U/DMA does CRC

Ben.