Jens Axboe wrote:

On Fri, Jul 16 2004, Max T. Woodbury wrote:

quoted

"Eric D. Mudama" wrote:

quoted

On Mon, Jul 12 at 13:52, Max T. Woodbury wrote:

quoted

Still, why would PIO mode be unsafe?  (I can see slower, but I don't
expect speed from this beast.  Oh well.  Thanks for the pointer.)

PIO has no data integrity check, so bogus cables that glitch the data
will not be detected.  Not sure if that is what he was talking about,
but is definitely a problem for PIO.

Huh? Unless something major has changed since the last time I looked at
DMA hardware (and it has been a few years), DMA uses the same transfer
sequence from the devices point of view as PIO.  The fact that the
transfer is under the control of another device rather than a program
should be transparent to the target device.  Impedance mismatches,
reflections and constructive and destructive interference caused by
cable problems don't care about who's in control of the busses.

I can see a possible problem with cache consistency causing problems
with PIO, but there are similar (abet in some sense inverted or
reversed) problems with DMA.

Yes that's very clever of you. But read what Eric writes - PIO has no
data integrity check. DMA transfers are crc'ed so you know if something
goes bad between device and host in the data phase, with PIO you do not.

Sorry, NO.  From the device point of view, DMA and PIO are indistinguishable.
Both have CRCs on some busses and neither have CRCs on others.  There are
ALWAYS CRCs on transfers across the drive interface cables.  This is controlled
by the IDE/CPU interface chip and not by the DMA hardware.  The transfer of
the CRC is triggered by the termination of data transfer which happens with
both DMA and PIO.  These are design issues that go back at least thirty
years and are generally well understood.

Bartlomiej was talking about timing register setup problems.  They can be
messed up for either mode.  They are separate for DMA and PIO.  His point
was that the default driver left PIO timing setup to the hardware and BIOS
while the special drivers sometimes included more specific initialization.
These are fairly new problems arising from multi-tiered bus technologies
like PCI.

max