[PATCH hyperv-next v5 07/11] dt-bindings: microsoft,vmbus: Add interrupts and DMA coherence
From: Roman Kisel <hidden>
Date: 2025-03-07 22:03:08
Also in:
kvmarm, linux-acpi, linux-arch, linux-arm-kernel, linux-devicetree, linux-pci, lkml
Subsystem:
hyper-v/azure core and drivers, open firmware and flattened device tree bindings, the rest · Maintainers:
"K. Y. Srinivasan", Haiyang Zhang, Wei Liu, Dexuan Cui, Long Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
To boot on ARM64, VMBus requires configuring interrupts. Missing DMA coherence property is sub-optimal as the VMBus transations are cache-coherent. Add interrupts to be able to boot on ARM64. Add DMA coherence to avoid doing extra work on maintaining caches on ARM64. Signed-off-by: Roman Kisel <redacted> --- .../devicetree/bindings/bus/microsoft,vmbus.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/bus/microsoft,vmbus.yaml b/Documentation/devicetree/bindings/bus/microsoft,vmbus.yaml
index a8d40c766dcd..3ab7d0116626 100644
--- a/Documentation/devicetree/bindings/bus/microsoft,vmbus.yaml
+++ b/Documentation/devicetree/bindings/bus/microsoft,vmbus.yaml@@ -28,13 +28,16 @@ properties: required: - compatible - ranges + - interrupts - '#address-cells' - '#size-cells' -additionalProperties: false +additionalProperties: true examples: - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> soc { #address-cells = <2>; #size-cells = <1>;
@@ -49,6 +52,9 @@ examples: #address-cells = <2>; #size-cells = <1>; ranges = <0x0f 0xf0000000 0x0f 0xf0000000 0x10000000>; + dma-coherent; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 2 IRQ_TYPE_EDGE_RISING>; }; }; };
--
2.43.0