[PATCH v3 5/5] arm64: dts: qcom: qcs6490-rb3gen2: Enable TC9563 embedded GPIO controller
From: Lorenzo Bianconi <hidden>
Date: 2026-09-04 17:16:25
Also in:
linux-arm-msm, linux-devicetree, linux-pci
Subsystem:
arm/qualcomm mailing list, arm/qualcomm support, the rest · Maintainers:
Bjorn Andersson, Konrad Dybcio, Linus Torvalds
The Toshiba TC9563 PCIe switch embeds a GPIO controller providing 37 GPIO lines. The controller is registered as an auxiliary device by the TC9563 power controller and accessed through the same i2c device. Describe the switch node itself as the embedded GPIO controller and us it to drive the PERST# reset lines of the two external downstream port (pcie@1,0 and pcie@2,0), as expected by the TC9563 power controller after switching to the GPIO descriptor API for per-port resets. Reviewed-by: Konrad Dybcio <redacted> Reviewed-by: Bartosz Golaszewski <redacted> Reviewed-by: Abel Vesa <redacted> Signed-off-by: Lorenzo Bianconi <redacted> --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index a13315bf0fb0..4da7342ca90d 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts@@ -867,7 +867,7 @@ &pcie1_phy { &pcie1_port0 { reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - pcie@0,0 { + tc9563: pcie@0,0 { compatible = "pci1179,0623"; reg = <0x10000 0x0 0x0 0x0 0x0>; #address-cells = <3>;
@@ -891,6 +891,9 @@ pcie@0,0 { pinctrl-0 = <&tc9563_resx_n>; pinctrl-names = "default"; + gpio-controller; + #gpio-cells = <2>; + pcie1_switch0_dsp1: pcie@1,0 { reg = <0x20800 0x0 0x0 0x0 0x0>; #address-cells = <3>;
@@ -899,6 +902,7 @@ pcie1_switch0_dsp1: pcie@1,0 { device_type = "pci"; ranges; bus-range = <0x3 0xff>; + reset-gpios = <&tc9563 2 GPIO_ACTIVE_LOW>; }; pcie@2,0 {
@@ -909,6 +913,7 @@ pcie@2,0 { device_type = "pci"; ranges; bus-range = <0x4 0xff>; + reset-gpios = <&tc9563 3 GPIO_ACTIVE_LOW>; /* Renesas μPD720201 PCIe USB3.0 Host Controller */ usb-controller@0,0 {
--
2.55.0