October 2026
11 messages across 7 threads.
| Last | Thread | Replies |
|---|---|---|
| Thursday 29 October | ||
| [PATCH] fpga: dfl: afu: prevent read-only region mappings from becoming writable
bo cao
|
none | |
| Wednesday 28 October | ||
| [PATCH v2] fpga: altera-cvp: Add Agilex5 CVP credit register support
tze.yee.ng@altera.com
|
none | |
| Friday 23 October | ||
| [PATCH v2] fpga: dfl: afu: prevent read-only port mappings from becoming writable
Abdifatah Suruur
|
none | |
| Tuesday 20 October | ||
| [PATCH 0/3] fpga: stratix10-soc: harden wait, ERROR order, and timeout
Adrian Ng Ho Yin
SUPERSEDED
|
4 | |
| Friday 9 October | ||
| [GIT PULL] FPGA Manager changes for 7.4-rc1
Xu Yilun
|
1 | |
| Tuesday 6 October | ||
| [PATCH v3] fpga: altera-freeze-bridge: clear all illegal request bits
tze.yee.ng@altera.com
|
none | |
| Friday 2 October | ||
| [PATCH v2] fpga: bridge: incorrect set to clear freeze_illegal_request register
tze.yee.ng@altera.com
|
1 | |