Re: [PATCH v11 01/10] dt-bindings: mediatek,dp: Add Display Port binding

On Thu, Jun 16, 2022 at 09:22:16PM +0800, Rex-BC Chen wrote:

On Tue, 2022-06-14 at 14:23 -0600, Rob Herring wrote:

quoted

On Fri, Jun 10, 2022 at 06:55:13PM +0800, Bo-Chen Chen wrote:

quoted

From: Markus Schneider-Pargmann <msp@baylibre.com>

This controller is present on several mediatek hardware. Currently
mt8195 and mt8395 have this controller without a functional
difference,
so only one compatible field is added.

The controller can have two forms, as a normal display port and as
an
embedded display port.

Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Signed-off-by: Guillaume Ranquet <redacted>
[Bo-Chen: Fix reviewers' comment]
Signed-off-by: Bo-Chen Chen <redacted>
---
 .../display/mediatek/mediatek,dp.yaml         | 101
++++++++++++++++++
 1 file changed, 101 insertions(+)
 create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml

diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya
ml
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya
ml
new file mode 100644
index 000000000000..10f50a0dcf49

--- /dev/null
+++

b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya
ml

@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: 

https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml*__;Iw!!CTRNKA9wMg0ARbw!yqAl1KhfbHqHN7-5aeqhzqeOVhPU_Z5beko5q-y-s5pcfp1WL5oVGvY5UF4EfWm4PWjc5mjBwyBUMsr_RI45ipbhsw$
 
+$schema: 
https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!yqAl1KhfbHqHN7-5aeqhzqeOVhPU_Z5beko5q-y-s5pcfp1WL5oVGvY5UF4EfWm4PWjc5mjBwyBUMsr_RI5WzYKENQ$
 
+
+title: MediaTek Display Port Controller
+
+maintainers:
+  - Chun-Kuang Hu [off-list ref]
+  - Jitao shi [off-list ref]
+
+description: |
+  Device tree bindings for the MediaTek display port and
+  embedded display port controller present on some MediaTek SoCs.
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt8195-dp-tx
+      - mediatek,mt8195-edp-tx
+
+  reg:
+    maxItems: 1
+
+  nvmem-cells:
+    maxItems: 1
+    description: efuse data for display port calibration
+
+  nvmem-cell-names:
+    const: dp_calibration_data
+
+  power-domains:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Input endpoint of the controller, usually
dp_intf
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Output endpoint of the controller
+
+    required:
+      - port@0
+      - port@1
+
+  max-lanes:
+    maxItems: 1
+    description: maximum number of lanes supported by the
hardware.

We already have a 'data-lanes' property defined in 
'video-interfaces.yaml' that can serve this purpose.

Hello Rob,

Thanks for review.
From the description of video-interfaces.yaml, I think it's not quite
match what we need. We only need this value be one of "1,2,4".

data-lanes = <0>;
data-lanes = <0 1>;
data-lanes = <0 1 2 3>;

Limiting the number of lanes to something less than the max is exactly 
how this property is used in addition to being able to show the mapping 
of lanes.

Rob