Re: Problem with FB
From: Nicolas Ferre <hidden>
Date: 2007-05-28 15:19:10
Diego A. Fons :
I was changing the timings values but it seems to get worse, with a set of values the screen moves with every ftp command thet sftp sends! Now the values are (it doesn't work either): #define AT91_DM9000_NWE_SETUP (8 << 0) #define AT91_DM9000_NCS_WR_SETUP (4 << 8) #define AT91_DM9000_NRD_SETUP (8 << 16) #define AT91_DM9000_NCS_RD_SETUP (4 << 24) #define AT91_DM9000_NWE_PULSE (16 << 0) #define AT91_DM9000_NCS_WR_PULSE (32 << 8) #define AT91_DM9000_NRD_PULSE (16 << 16) #define AT91_DM9000_NCS_RD_PULSE (32 << 24) #define AT91_DM9000_NWE_CYCLE (36 << 0) #define AT91_DM9000_NRD_CYCLE (36 << 16) #define AT91_DM9000_TDF (1 << 16) I test it with lower and higher values and nothing (with 1 and 127). Can you tell me how is it possible that the DM9000 timings interfere with the frame buffer?
Well they both use the SDRam/EBI interface (in fact the ARM926 and the LCD) and they may be in conflict some time to get the internal AHB bus (H matrix). The idea is that one or the other master takes the bus for too long. What can help us is if you can also check if the fifo underflow UFLWIS bit (#4) rises during LDC use. So, if the LCD is interrupted during a data burst from sdram, it can have difficulties to resume its transfer. You can try to lower the configured burst length on the LCD : ATMEL_LCDC_DMA_BURST_LEN = 4 (so the register field must be written with 0x3) instead of 8. Another option will be to keep the burst length and increase the slot cycle in the Matrix interface (from 16->32 or 64). It is the preferred one. This is done in the AT91bootstrap but you can do it for testing using a jtag ice. Keep me informed, Cheers, -- Nicolas Ferre ------------------------------------------------------------------------- This SF.net email is sponsored by DB2 Express Download DB2 Express C - the FREE version of DB2 express and take control of your XML. No limits. Just data. Click to get it now. http://sourceforge.net/powerbar/db2/