[PATCH 5/6] arm64: dts: qcom: kodiak: use thermal hw-bin trips
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HOTtoday
From: Gaurav Kohli <hidden>
Date: 2026-10-02 10:47:48
Also in:
linux-arm-msm, linux-devicetree, linux-pm, lkml
Subsystem:
arm/qualcomm mailing list, arm/qualcomm support, the rest · Maintainers:
Bjorn Andersson, Konrad Dybcio, Linus Torvalds
From: Amit Kucheria <redacted> kodiak-based SoCs are binned at manufacturing time, with the bin computed from the jtag-id and feat-id qfprom fuses. The tsens driver now reads these and feeds the resulting bin to the thermal core, which selects per-bin trip temperatures. Add the jtag-id and feat-id nvmem cells to the tsens nodes and convert the passive mitigation trip points from a fixed 95C to per-bin values (95C for bin 0x1, 105C for bin 0x2) using the new temperature-bin/thermal-hw-bin properties. Signed-off-by: Amit Kucheria <redacted> Co-developed-by: Gaurav Kohli <redacted> Signed-off-by: Gaurav Kohli <redacted> --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 56 +++++++++++++++++++++++++++--------- 1 file changed, 42 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 347815e5983e..f3bb9cd8f393 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi@@ -1019,6 +1019,16 @@ gpu_speed_bin: gpu-speed-bin@1e9 { reg = <0x1e9 0x2>; bits = <5 8>; }; + jtag_id: jtag-id@180 { + reg = <0x180 0x4>; + /* bits = <offset width>: 20 bits at offset 0 */ + bits = <0 20>; + }; + feat_id: feat-id@180 { + reg = <0x180 0x4>; + /* bits = <offset width>: 8 bits at offset 20 */ + bits = <20 8>; + }; }; sdhc_1: mmc@7c4000 {
@@ -5782,6 +5792,8 @@ tsens0: thermal-sensor@c263000 { compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; reg = <0 0x0c263000 0 0x1ff>, /* TM */ <0 0x0c222000 0 0x1ff>; /* SROT */ + nvmem-cells = <&jtag_id>, <&feat_id>; + nvmem-cell-names = "jtag-id", "feat-id"; #qcom,sensors = <15>; interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
@@ -5793,6 +5805,8 @@ tsens1: thermal-sensor@c265000 { compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; reg = <0 0x0c265000 0 0x1ff>, /* TM */ <0 0x0c223000 0 0x1ff>; /* SROT */ + nvmem-cells = <&jtag_id>, <&feat_id>; + nvmem-cell-names = "jtag-id", "feat-id"; #qcom,sensors = <12>; interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
@@ -7136,7 +7150,8 @@ cpu0_alert0: trip-point0 { }; cpu0_alert1: trip-point1 { - temperature = <95000>; + temperature-bin = <95000 105000>; + thermal-hw-bin = <0x1>, <0x2>; hysteresis = <2000>; type = "passive"; };
@@ -7179,7 +7194,8 @@ cpu1_alert0: trip-point0 { }; cpu1_alert1: trip-point1 { - temperature = <95000>; + temperature-bin = <95000 105000>; + thermal-hw-bin = <0x1>, <0x2>; hysteresis = <2000>; type = "passive"; };
@@ -7222,7 +7238,8 @@ cpu2_alert0: trip-point0 { }; cpu2_alert1: trip-point1 { - temperature = <95000>; + temperature-bin = <95000 105000>; + thermal-hw-bin = <0x1>, <0x2>; hysteresis = <2000>; type = "passive"; };
@@ -7265,7 +7282,8 @@ cpu3_alert0: trip-point0 { }; cpu3_alert1: trip-point1 { - temperature = <95000>; + temperature-bin = <95000 105000>; + thermal-hw-bin = <0x1>, <0x2>; hysteresis = <2000>; type = "passive"; };
@@ -7308,7 +7326,8 @@ cpu4_alert0: trip-point0 { }; cpu4_alert1: trip-point1 { - temperature = <95000>; + temperature-bin = <95000 105000>; + thermal-hw-bin = <0x1>, <0x2>; hysteresis = <2000>; type = "passive"; };
@@ -7351,7 +7370,8 @@ cpu5_alert0: trip-point0 { }; cpu5_alert1: trip-point1 { - temperature = <95000>; + temperature-bin = <95000 105000>; + thermal-hw-bin = <0x1>, <0x2>; hysteresis = <2000>; type = "passive"; };
@@ -7394,7 +7414,8 @@ cpu6_alert0: trip-point0 { }; cpu6_alert1: trip-point1 { - temperature = <95000>; + temperature-bin = <95000 105000>; + thermal-hw-bin = <0x1>, <0x2>; hysteresis = <2000>; type = "passive"; };
@@ -7437,7 +7458,8 @@ cpu7_alert0: trip-point0 { }; cpu7_alert1: trip-point1 { - temperature = <95000>; + temperature-bin = <95000 105000>; + thermal-hw-bin = <0x1>, <0x2>; hysteresis = <2000>; type = "passive"; };
@@ -7480,7 +7502,8 @@ cpu8_alert0: trip-point0 { }; cpu8_alert1: trip-point1 { - temperature = <95000>; + temperature-bin = <95000 105000>; + thermal-hw-bin = <0x1>, <0x2>; hysteresis = <2000>; type = "passive"; };
@@ -7523,7 +7546,8 @@ cpu9_alert0: trip-point0 { }; cpu9_alert1: trip-point1 { - temperature = <95000>; + temperature-bin = <95000 105000>; + thermal-hw-bin = <0x1>, <0x2>; hysteresis = <2000>; type = "passive"; };
@@ -7566,7 +7590,8 @@ cpu10_alert0: trip-point0 { }; cpu10_alert1: trip-point1 { - temperature = <95000>; + temperature-bin = <95000 105000>; + thermal-hw-bin = <0x1>, <0x2>; hysteresis = <2000>; type = "passive"; };
@@ -7609,7 +7634,8 @@ cpu11_alert0: trip-point0 { }; cpu11_alert1: trip-point1 { - temperature = <95000>; + temperature-bin = <95000 105000>; + thermal-hw-bin = <0x1>, <0x2>; hysteresis = <2000>; type = "passive"; };
@@ -7724,7 +7750,8 @@ gpuss0-thermal { trips { gpuss0_alert0: trip-point0 { - temperature = <95000>; + temperature-bin = <95000 105000>; + thermal-hw-bin = <0x1>, <0x2>; hysteresis = <2000>; type = "passive"; };
@@ -7751,7 +7778,8 @@ gpuss1-thermal { trips { gpuss1_alert0: trip-point0 { - temperature = <95000>; + temperature-bin = <95000 105000>; + thermal-hw-bin = <0x1>, <0x2>; hysteresis = <2000>; type = "passive"; };
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2.34.1