[PATCH 3/4] clk: qcom: gcc-glymur: Use clk_regmap_phy_mux_ops for GCC UFS muxes
From: Jagadeesh Kona <hidden>
Date: 2026-09-04 18:51:14
Also in:
linux-arm-msm, linux-clk, lkml
Subsystem:
arm/qualcomm mailing list, common clk framework, qualcomm clock drivers, the rest · Maintainers:
Stephen Boyd, Brian Masney, Jerome Brunet, Bjorn Andersson, Linus Torvalds
Use clk_regmap_phy_mux_ops for GCC UFS muxes so these muxes are
automatically switched to UFS external symbol clocks during enable and
safely parked at XO clk during disable.
Fixes: efe504300a17 ("clk: qcom: gcc: Add support for Global Clock Controller")
Signed-off-by: Jagadeesh Kona <redacted>
---
drivers/clk/qcom/gcc-glymur.c | 69 +++++++++++--------------------------------
1 file changed, 18 insertions(+), 51 deletions(-)
diff --git a/drivers/clk/qcom/gcc-glymur.c b/drivers/clk/qcom/gcc-glymur.c
index 2ee4820b6fdfb1ad2cdb15366cf746651fc1a36a..a47a2c6b961ba01edc69be91e299a190f4662c3e 100644
--- a/drivers/clk/qcom/gcc-glymur.c
+++ b/drivers/clk/qcom/gcc-glymur.c@@ -481,36 +481,6 @@ static const struct clk_parent_data gcc_parent_data_17[] = { { .hw = &gcc_gpll0_out_even.clkr.hw }, }; -static const struct parent_map gcc_parent_map_18[] = { - { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_18[] = { - { .index = DT_UFS_PHY_RX_SYMBOL_0_CLK }, - { .index = DT_BI_TCXO }, -}; - -static const struct parent_map gcc_parent_map_19[] = { - { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_19[] = { - { .index = DT_UFS_PHY_RX_SYMBOL_1_CLK }, - { .index = DT_BI_TCXO }, -}; - -static const struct parent_map gcc_parent_map_20[] = { - { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_20[] = { - { .index = DT_UFS_PHY_TX_SYMBOL_0_CLK }, - { .index = DT_BI_TCXO }, -}; - static const struct parent_map gcc_parent_map_21[] = { { P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 }, { P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
@@ -907,47 +877,44 @@ static struct clk_regmap_phy_mux gcc_pcie_6_pipe_clk_src = { }, }; -static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { +static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_0_clk_src = { .reg = 0x7706c, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_18, .clkr = { .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_rx_symbol_0_clk_src", - .parent_data = gcc_parent_data_18, - .num_parents = ARRAY_SIZE(gcc_parent_data_18), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .index = DT_UFS_PHY_RX_SYMBOL_0_CLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, }, }, }; -static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = { +static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_1_clk_src = { .reg = 0x770f0, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_19, .clkr = { .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_rx_symbol_1_clk_src", - .parent_data = gcc_parent_data_19, - .num_parents = ARRAY_SIZE(gcc_parent_data_19), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .index = DT_UFS_PHY_RX_SYMBOL_1_CLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, }, }, }; -static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = { +static struct clk_regmap_phy_mux gcc_ufs_phy_tx_symbol_0_clk_src = { .reg = 0x7705c, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_20, .clkr = { .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_tx_symbol_0_clk_src", - .parent_data = gcc_parent_data_20, - .num_parents = ARRAY_SIZE(gcc_parent_data_20), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .index = DT_UFS_PHY_TX_SYMBOL_0_CLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, }, }, };
--
2.34.1