The dc8200_pix0 and dc8200_pix1 MUXes feed the display controller, and
the rate they carry is ultimately produced by the HDMI PHY, which
registers hdmitx0_pixelclk as a clock provider.
Add CLK_SET_RATE_PARENT to both MUXes so a rate requested on them
reaches that parent, instead of being clamped to whatever rate the
parent already happens to run at.
Co-developed-by: Dominique Belhachemi <redacted>
Signed-off-by: Dominique Belhachemi <redacted>
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Sashiko has reviewed this patch and found no issues. It looks great!
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Sashiko AI review · https://sashiko.dev/#/patchset/20260904-jh7110-clean-send-v3-0-484f9ae72715@samsung.com?part=13