Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The clock names described in the commit message contradict the clock names defined in the schema.
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commit d8a94c9a1ba333a313d74a23f9f5fb6dcc401472
Author: Michal Wilczynski [off-list ref]
dt-bindings: display: bridge: Add starfive,jh7110-inno-hdmi-controller
This commit adds the device tree binding schema for the StarFive JH7110
Innosilicon HDMI controller.
It consumes register access clocks (sys, mclk, bclk) from the voutcrg and
both the pixel clock (pclk) and the PHY from its hdmi_phy sibling.
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diff --git a/Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno-hdmi-controller.yaml b/Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno-hdmi-controller.yaml
new file mode 100644
index 0000000000000..ea489a7722d02
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno-hdmi-controller.yaml
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+ clock-names:
+ items:
+ - const: pclk
+ - const: mclk
+ - const: bclk
+ - const: pixel
[Severity: Medium]
The clock names described in the commit message contradict the clock names
defined in the schema.
The commit message states that the device consumes register access clocks
"(sys, mclk, bclk)" and the pixel clock "(pclk)". However, the schema defines
the expected clock names as "pclk" for the main clock and "pixel" for the
pixel clock.
Is the commit message inaccurate, or should the schema use "sys" and "pclk"
instead of "pclk" and "pixel" for these respective clocks?
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Sashiko AI review · https://sashiko.dev/#/patchset/20260904-jh7110-clean-send-v3-0-484f9ae72715@samsung.com?part=2