[PATCH v7 9/9] arm64: dts: freescale: imx95: Add video codec node
From: Nas Chung <nas.chung@chipsnmedia.com>
Date: 2026-09-04 06:47:44
Also in:
linux-arm-kernel, linux-media, lkml
Subsystem:
arm/freescale imx / mxc / layerscape arm architecture, the rest · Maintainers:
Frank Li, Sascha Hauer, Linus Torvalds
Add the Chips and Media wave633 video codec node on IMX95 SoCs. Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com> --- .../boot/dts/freescale/imx95-19x19-evk.dts | 10 +++++ arch/arm64/boot/dts/freescale/imx95.dtsi | 37 +++++++++++++++++++ 2 files changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
index 814da90243b2..7e90a63f0341 100644
--- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts@@ -112,6 +112,11 @@ vdev0buffer: vdev0buffer@88020000 { reg = <0 0x88020000 0 0x100000>; no-map; }; + + vpu_boot: memory@a0000000 { + reg = <0 0xa0000000 0 0x100000>; + no-map; + }; }; flexcan1_phy: can-phy0 {
@@ -1198,3 +1203,8 @@ &tpm6 { pinctrl-0 = <&pinctrl_tpm6>; status = "okay"; }; + +&vpu { + memory-region = <&vpu_boot>; + status = "okay"; +};
diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index 38fc47024841..35b24f8c8742 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi@@ -2139,6 +2139,43 @@ vpu_blk_ctrl: clock-controller@4c410000 { assigned-clock-rates = <133333333>, <667000000>, <500000000>; }; + vpu: video-codec@4c4c0000 { + compatible = "nxp,imx95-vpu"; + reg = <0x0 0x4c4c0000 0x0 0x10000>; + clocks = <&scmi_clk IMX95_CLK_VPU>, + <&vpu_blk_ctrl IMX95_CLK_VPUBLK_WAVE>; + clock-names = "core", "vpublk"; + power-domains = <&scmi_devpd IMX95_PD_VPU>, + <&scmi_perf IMX95_PERF_VPU>; + power-domain-names = "vpu", "perf"; + sram = <&sram1>; + #cooling-cells = <2>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + interface@4c480000 { + reg = <0x0 0x4c480000 0x0 0x10000>; + interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; + }; + + interface@4c490000 { + reg = <0x0 0x4c490000 0x0 0x10000>; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + }; + + interface@4c4a0000 { + reg = <0x0 0x4c4a0000 0x0 0x10000>; + interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; + }; + + interface@4c4b0000 { + reg = <0x0 0x4c4b0000 0x0 0x10000>; + interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + jpegdec: jpegdec@4c500000 { compatible = "nxp,imx95-jpgdec", "nxp,imx8qxp-jpgdec"; reg = <0x0 0x4C500000 0x0 0x00050000>;
--
2.31.1