[PATCH v3 9/9] arm64: dts: freescale: imx95: Add video codec node
From: Nas Chung <nas.chung@chipsnmedia.com>
Date: 2025-08-29 08:47:42
Also in:
linux-devicetree, linux-media, lkml
Subsystem:
arm/freescale imx / mxc arm architecture, the rest, tq systems board & driver support · Maintainers:
Frank Li, Sascha Hauer, Linus Torvalds
Add the Chips and Media wave633 video codec node on IMX95 SoCs. Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com> --- .../boot/dts/freescale/imx95-15x15-evk.dts | 5 +++ .../boot/dts/freescale/imx95-19x19-evk.dts | 10 +++++ .../dts/freescale/imx95-phycore-fpsc.dtsi | 10 +++++ .../boot/dts/freescale/imx95-tqma9596sa.dtsi | 5 +++ arch/arm64/boot/dts/freescale/imx95.dtsi | 43 +++++++++++++++++++ 5 files changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
index 46f6e0fbf2b0..07e070ae92b7 100644
--- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts@@ -1137,6 +1137,11 @@ &wdog3 { status = "okay"; }; +&vpu { + memory-region = <&vpu_boot>; + sram = <&sram1>; +}; + &xcvr { clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&scmi_clk IMX95_CLK_SPDIF>,
diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
index 2f949a0d48d2..c9d8b78d5768 100644
--- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts@@ -75,6 +75,11 @@ linux_cma: linux,cma { linux,cma-default; reusable; }; + + vpu_boot: vpu_boot@a0000000 { + reg = <0 0xa0000000 0 0x100000>; + no-map; + }; }; flexcan1_phy: can-phy0 {
@@ -1044,3 +1049,8 @@ &tpm6 { pinctrl-0 = <&pinctrl_tpm6>; status = "okay"; }; + +&vpu { + memory-region = <&vpu_boot>; + sram = <&sram1>; +};
diff --git a/arch/arm64/boot/dts/freescale/imx95-phycore-fpsc.dtsi b/arch/arm64/boot/dts/freescale/imx95-phycore-fpsc.dtsi
index 7519d5bd06ba..73c84ab60dfd 100644
--- a/arch/arm64/boot/dts/freescale/imx95-phycore-fpsc.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95-phycore-fpsc.dtsi@@ -59,6 +59,11 @@ linux,cma { size = <0 0x3c000000>; linux,cma-default; }; + + vpu_boot: vpu_boot@a0000000 { + reg = <0 0xa0000000 0 0x100000>; + no-map; + }; }; };
@@ -654,3 +659,8 @@ &usdhc3 { /* FPSC SDIO */ pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-names = "default"; }; + +&vpu { + memory-region = <&vpu_boot>; + sram = <&sram1>; +};
diff --git a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi
index 180124cc5bce..f7c7e676a077 100644
--- a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi@@ -696,3 +696,8 @@ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>; }; }; + +&vpu { + memory-region = <&vpu_boot>; + sram = <&sram1>; +};
diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index 4ca6a7ea586e..4c14bf9437b8 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi@@ -1820,6 +1820,49 @@ vpu_blk_ctrl: clock-controller@4c410000 { assigned-clock-rates = <133333333>, <667000000>, <500000000>; }; + vpu: video-codec@4c4c0000 { + compatible = "nxp,imx95-vpu"; + reg = <0x0 0x4c4c0000 0x0 0x10000>; + clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_WAVE>; + power-domains = <&scmi_perf IMX95_PERF_VPU>; + #cooling-cells = <2>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + vpucore0: video-core@4c480000 { + compatible = "nxp,imx95-vpu-core"; + reg = <0x0 0x4c480000 0x0 0x10000>; + clocks = <&scmi_clk IMX95_CLK_VPU>; + power-domains = <&scmi_devpd IMX95_PD_VPU>; + interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; + }; + + vpucore1: video-core@4c490000 { + compatible = "nxp,imx95-vpu-core"; + reg = <0x0 0x4c490000 0x0 0x10000>; + clocks = <&scmi_clk IMX95_CLK_VPU>; + power-domains = <&scmi_devpd IMX95_PD_VPU>; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + }; + + vpucore2: video-core@4c4a0000 { + compatible = "nxp,imx95-vpu-core"; + reg = <0x0 0x4c4a0000 0x0 0x10000>; + clocks = <&scmi_clk IMX95_CLK_VPU>; + power-domains = <&scmi_devpd IMX95_PD_VPU>; + interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; + }; + + vpucore3: video-core@4c4b0000 { + compatible = "nxp,imx95-vpu-core"; + reg = <0x0 0x4c4b0000 0x0 0x10000>; + clocks = <&scmi_clk IMX95_CLK_VPU>; + power-domains = <&scmi_devpd IMX95_PD_VPU>; + interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + jpegdec: jpegdec@4c500000 { compatible = "nxp,imx95-jpgdec", "nxp,imx8qxp-jpgdec"; reg = <0x0 0x4C500000 0x0 0x00050000>;
--
2.31.1