[PATCH 4/4] clk: meson: t7: don't mark sys_ampipe_nand as critical
flat view
COLD39d
SUPERSEDED
From: Lucas Tanure <hidden>
Date: 2026-09-03 22:59:39
Also in:
linux-amlogic, linux-arm-kernel, linux-clk, linux-mmc, lkml
Subsystem:
arm/amlogic meson soc clock framework, common clk framework, the rest · Maintainers:
Neil Armstrong, Jerome Brunet, Stephen Boyd, Brian Masney, Jerome Brunet, Linus Torvalds
Revision v1 of 2 in this series.
Revisions (2)
- v1 current
- v2 [diff vs current]
sys_ampipe_nand clocks the pipeline stage inserted in the bus path
between the SD/eMMC controllers and the NIC_MATRIX fabric. It does have
identifiable consumers - the three MMC controllers - so marking it
critical was the wrong tool: the clock should be referenced from the
consumer nodes and claimed by the mmc driver instead.
Drop the CLK_IS_CRITICAL flag and update the comment accordingly.
sys_am2axi0..2 remain critical as they clock the AXI DMA bus itself and
have no single identifiable consumer.
This depends on the MMC controllers actually referencing the clock:
the dt-bindings, mmc driver and t7 DTS changes adding the "pipeline"
clock must land before this one, otherwise the boot hangs and memory
corruption this clock caused are reintroduced.
Fixes: 43e1705ecab9 ("clk: meson: t7: keep the memory fabric clocks running")
Assisted-by: Claude Fable 5 [off-list ref]
Signed-off-by: Lucas Tanure <redacted>
---
drivers/clk/meson/t7-peripherals.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/meson/t7-peripherals.c b/drivers/clk/meson/t7-peripherals.c
index 55d09e78593b..2f429ea86796 100644
--- a/drivers/clk/meson/t7-peripherals.c
+++ b/drivers/clk/meson/t7-peripherals.c@@ -945,13 +945,13 @@ static T7_SYS_PCLK(sys_aucpu, SYS_CLK_EN0_REG0, 14, 0); static T7_SYS_PCLK(sys_cec, SYS_CLK_EN0_REG0, 16, 0); static T7_SYS_PCLK(sys_gdc, SYS_CLK_EN0_REG0, 17, 0); static T7_SYS_PCLK(sys_deswarp, SYS_CLK_EN0_REG0, 18, 0); +static T7_SYS_PCLK(sys_ampipe_nand, SYS_CLK_EN0_REG0, 19, 0); +static T7_SYS_PCLK(sys_ampipe_eth, SYS_CLK_EN0_REG0, 20, 0); /* - * NOTE: sys_ampipe_nand and sys_am2axi0..2 provide the clock to the AXI bus - * used for DMA between the peripherals and the DRAM. After the clocks are - * disabled, a device that starts a transfer cannot complete it. + * NOTE: sys_am2axi0..2 provide the clock to the AXI bus used for DMA between + * the peripherals and the DRAM. After the clocks are disabled, a device that + * starts a transfer cannot complete it. */ -static T7_SYS_PCLK(sys_ampipe_nand, SYS_CLK_EN0_REG0, 19, CLK_IS_CRITICAL); -static T7_SYS_PCLK(sys_ampipe_eth, SYS_CLK_EN0_REG0, 20, 0); static T7_SYS_PCLK(sys_am2axi0, SYS_CLK_EN0_REG0, 21, CLK_IS_CRITICAL); static T7_SYS_PCLK(sys_am2axi1, SYS_CLK_EN0_REG0, 22, CLK_IS_CRITICAL); static T7_SYS_PCLK(sys_am2axi2, SYS_CLK_EN0_REG0, 23, CLK_IS_CRITICAL);
--
2.55.0