Re: [PATCH 11/12] riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree

On 2026-08-24 15:02 +0200, Andrew Lunn wrote:

quoted

+&ethernet {
+	phy-handle = <&phy0>;
+	/*
+	 * YT8531 RGMII timing on this board requires no PHY internal delays.

Please extend this sentence with an explanation why it needs no delay?

There are times this is correct, but it is also mostly wrong. Without
an explanation, i cannot say if this is correct or not.

Thanks for the review.

The DP1000 SoC integration provides the required TX and RX RGMII clock
skew, so enabling the YT8531 internal delays would apply the delay twice.

I will clarify this in the next version.

   Andrew

Best regards,
Jia Wang