[PATCH v6 09/10] arm64: dts: renesas: r9a08g046: Add USB2.0 device nodes
COLD51d
From: Biju <hidden>
Date: 2026-08-06 10:22:49
Also in:
linux-renesas-soc, lkml
Subsystem:
arm/risc-v/renesas architecture, the rest · Maintainers:
Geert Uytterhoeven, Magnus Damm, Linus Torvalds
Revision v6 of 7 in this series.
Revisions (7)
From: Biju Das <biju.das.jz@bp.renesas.com> Add USB2.0 device nodes to the RZ/G3L (r9a08g046) SoC DTSI, covering the USB PHY controller, OHCI/EHCI host controllers, and USB2 PHYs for both ports. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- v5->v6: * No change v4->v5: * Dropped renesas,sysc-pwrrdy property. v3->v4: * No change v2->v3: * No change v1->v2: * Updated commit description. * Added regulators group node and its children. --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 104 +++++++++++++++++++++ 1 file changed, 104 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index 85e409ac8d5c..bf0dbac66d14 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi@@ -1198,6 +1198,110 @@ queue3 { }; }; + phyrst: usbphy-ctrl@11e00000 { + compatible = "renesas,r9a08g046-usbphy-ctrl"; + reg = <0 0x11e00000 0 0x10000>; + clocks = <&cpg CPG_MOD R9A08G046_USB_PCLK>; + resets = <&cpg R9A08G046_USB_PRESETN>; + power-domains = <&cpg>; + #reset-cells = <1>; + status = "disabled"; + + regulators { + usb0_vbus_otg: vbus0 { + regulator-name = "usb0_vbus"; + }; + + usb1_vbus_otg: vbus1 { + regulator-name = "usb1_vbus"; + }; + }; + }; + + ohci0: usb@11e10000 { + compatible = "generic-ohci"; + reg = <0 0x11e10000 0 0x100>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A08G046_USB_PCLK>, + <&cpg CPG_MOD R9A08G046_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G046_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ohci1: usb@11e90000 { + compatible = "generic-ohci"; + reg = <0 0x11e90000 0 0x100>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A08G046_USB_PCLK>, + <&cpg CPG_MOD R9A08G046_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A08G046_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci0: usb@11e10100 { + compatible = "generic-ehci"; + reg = <0 0x11e10100 0 0x100>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A08G046_USB_PCLK>, + <&cpg CPG_MOD R9A08G046_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G046_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci1: usb@11e90100 { + compatible = "generic-ehci"; + reg = <0 0x11e90100 0 0x100>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A08G046_USB_PCLK>, + <&cpg CPG_MOD R9A08G046_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A08G046_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@11e10200 { + compatible = "renesas,usb2-phy-r9a08g046"; + reg = <0 0x11e10200 0 0x700>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A08G046_USB_PCLK>, + <&cpg CPG_MOD R9A08G046_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G046_USB_U2H0_HRESETN>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@11e90200 { + compatible = "renesas,usb2-phy-r9a08g046"; + reg = <0 0x11e90200 0 0x700>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A08G046_USB_PCLK>, + <&cpg CPG_MOD R9A08G046_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A08G046_USB_U2H1_HRESETN>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; + }; + pcie: pcie@11e40000 { reg = <0 0x11e40000 0 0x10000>; ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>;
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2.43.0