On 6/9/26 12:00 AM, Rob Herring wrote:
On Sat, Jun 6, 2026 at 6:21 AM Dmitry Baryshkov
[off-list ref] wrote:
quoted
On Fri, Jun 05, 2026 at 02:06:38PM -0500, Rob Herring wrote:
quoted
On Tue, Jun 02, 2026 at 11:12:34AM +1200, Oliver White wrote:
quoted
Add the documentation for the 'snps,reinit-phy-on-resume' boolean
property. When set, the DWC3 core will perform a full phy_exit() +
phy_init() cycle on each USB2 PHY during the host-mode fast resume
path. This is needed on platforms where the USB2 PHY power domain
is gated during deep sleep even when device_may_wakeup is true.
Signed-off-by: Oliver White <redacted>
---
.../devicetree/bindings/usb/snps,dwc3-common.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
index 6c0b8b653824..d12f6ae81ab8 100644
--- a/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
+++ b/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
@@ -212,6 +212,16 @@ properties:
When set, run the SOF/ITP counter based on ref_clk.
type: boolean
+ snps,reinit-phy-on-resume:
+ description:
+ When set, the DWC3 will re-initialize the USB2 PHYs during the
+ host-mode fast resume path (device_may_wakeup). Some platforms
+ cut PHY power during deep sleep even when USB wake is enabled,
+ and the standard PHY runtime PM resume is insufficient to restore
+ the PHY register state. This quirk forces a full phy_exit() +
+ phy_init() cycle on each USB2 PHY.
+ type: boolean
This should be implied from a platform specific compatible string.
Platform as in the "root node compatible"?
No, the SoC specific one in the node you are trying to add this property to.
Taking a step back, wouldn't this point to an issue in the PHY driver
itself?
Konrad