On Fri, 06 Mar 2026 15:34:07 +0100, John Madieu wrote:

The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
the existing RZ/G3S PCIe controller, but with several key differences.
This series adds support for the RZ/G3E PCIe controller by extending the existing
RZ/G3S driver and device tree bindings.

Key differences between RZ/G3E and RZ/G3S PCIe controllers:

[...]

Applied, thanks!

[01/15] PCI: rzg3s-host: Fix reset handling in probe error path
        commit: d284389d4576e7c8040dc4cbb66876e539c6d064
[02/15] PCI: rzg3s-host: Reorder reset assertion during suspend
        commit: 34735f63748daa2ea27544259c3042b4948376bf
[03/15] PCI: rzg3s-host: Rework inbound window algorithm for multi-SoC support
        commit: d17a200a747b01e05bb0fc14d62fbb5ad6653869
[05/15] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Fix naming properties
        commit: bb1b0f47f6822864c1689f46348efa42c5d4074c
[06/15] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3E SoC
        commit: fabce18494e5a4f388c70a40fa8351c911790d8d
[07/15] PCI: rzg3s-host: Make SYSC register offsets SoC-specific
        commit: 346dd3422ed9ff56f033726a50fad2da5677eb12
[08/15] PCI: rzg3s-host: Make configuration reset lines optional
        commit: 4ec4ccdaace40397638c305c0a36b423d2142a93
[09/15] PCI: rzg3s-host: Add SoC-specific configuration and initialization callbacks
        commit: 5f2c4de717786150f8d6cdbdbffb986cd3c59edb
[10/15] PCI: rzg3s-host: Explicitly set class code for RZ/G3E compatibility
        commit: 1e75d2e9a0e018b53f06dcc2e9345ac10f1aa174
[11/15] PCI: rzg3s-host: Add PCIe Gen3 (8.0 GT/s) link speed support
        commit: 5e9a5af5c9a2797a5e41e8ee565ce8108588f956
[12/15] PCI: rzg3s-host: Add support for RZ/G3E PCIe controller
        commit: 8197ec49a2062185f6bd432a19969ce0b3752e94

Best regards,
-- 
Manivannan Sadhasivam [off-list ref]