Hi John,

On Fri, Mar 6, 2026 at 2:39 PM John Madieu
[off-list ref] wrote:

The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
the existing RZ/G3S PCIe controller, but with several key differences.
This series adds support for the RZ/G3E PCIe controller by extending the existing
RZ/G3S driver and device tree bindings.

Key differences between RZ/G3E and RZ/G3S PCIe controllers:

Link Speed Support:
 - RZ/G3E: Supports PCIe Gen3 (8.0 GT/s) alongside Gen2 (5.0 GT/s)
 - RZ/G3S: Supports PCIe Gen2 (5.0 GT/s) only

Reset Control:
 - RZ/G3E: Uses register-based reset control mechanism
 - RZ/G3S: Uses exclusively external reset control signals

Inbound Window Configuration:
 - RZ/G3E: Requires precise power-of-2 window coverage with strict address
   alignment constraints. Non-power-of-2 memory regions must be split into
   multiple windows to avoid over-mapping, ensuring proper hardware address
   decoding for DMA operations.
 - RZ/G3S: Uses a simpler approach that rounds up to the next power-of-2,
   creating single larger windows. The hardware tolerates over-mapped regions.

Class/Revision IDs:
 - RZ/G3E: Requires explicit setting of class/revision values
 - RZ/G3S: Has default values in hardware

Clock Naming:
 - RZ/G3E: Uses "clkpmu" clock for power management
 - RZ/G3S: Uses "clkl1pm" PM control clock while CLKREQ_B is deasserting

Phy Settings:
 - RZ/G3E: Does not need PHY settings as it works with default hw values
 - RZ/G3S: Requires explicit PHY settings

This series extends the existing driver to detect the SoC type from the device
tree compatible string and configure the controller appropriately. The updates
are minimal and focused on the hardware-specific differences while keeping the
common code paths unified.

Changes:

v8:
 - Collected additional Rb tags on remaining code patches
 - Fixed typos in patch descriptions
 - Fixed checkpatch warnings

v7:
 - Removed former patch [04/16] adding support for init[off|asserted] clocks
   and resets as these steps are not required anymore
 - Renamed RZG3E_PCI_RESET* register defines to RZG3S_PCI_RESET* for
   consistency, as upcoming SoCs (RZ/V2H, RZ/T2N, RZ/N2H) share these
   registers
 - Dropped some useless comments and reduced verbose descriptions to
   concise forms
 - Unified function naming: rzg3s_pcie_config_{post_init,deinit}() and
   rzg3e_pcie_config_{pre_init,post_init,deinit}()
 - Used local mask variables in rzg3e_pcie_config_{pre_init,post_init}()
   for compactness within 80-char line limit
 - Fixed resume_noirq: reordered MODE before RST_RSM_B to match probe
   sequence, fixing error path handling
 - Fixed checkpatch commit message line length warnings

v6:
 - Replaced rzg3s_sysc_config() with enum-based rzg3s_sysc_config_func()
   as suggested by Claudiu, dropping the -1 skip pattern
 - Introduced enum rzg3s_sysc_func_id and array-based SYSC function
   descriptors in patch 08
 - Used regmap_update_bits() consistently for all SYSC accesses
 - Fixed config_reinit error path in suspend_noirq: call config_pre_init
   before config_post_init as spotted by Claudiu
 - Fixed double config_deinit in rzg3s_pcie_host_init() error path by
   separating config_deinit_post into a non-fall-through path
 - Shortened comments as per Claudiu's suggestions
 - Reordered patchset, moving v5's patch 09/16 to 02/16 and added Fixes tag

v5:
 - Introduced new patch to reorder reset handling
 - Introduced rzg3s_sysc_config() helper to handle SYS config
 - Collected Tags on documentation

v4:
 - Collected Ab tag
 - Fixed binding clock name constraint

v3:
 - Removed extra MaxItems in binding causing warnings
 - Fix potential crash for non-initialized rcdev in CPG driver
 - Fix binding contraints replacing 'description' with 'const' as per
   Geert and Rob's comment

v2:
 - Address Bjorn typo comments
 - Address Claidiu's comment on stylish
 - Use single inbound-window-configuration function for both G3E/G3S
 - Refactor goto laballing as per Claudiu's comments
 - Update bindings and reused G3S's interrupt ordering
   * This involves reordering interrupts in dt
 - Remove Board-specific PCIe dma-range.


John Madieu (15):
  PCI: rzg3s-host: Fix reset handling in probe error path
  PCI: rzg3s-host: Reorder reset assertion during suspend
  PCI: rzg3s-host: Rework inbound window algorithm for multi-SoC support
  clk: renesas: r9a09g047: Add PCIe clocks and reset
  dt-bindings: PCI: renesas,r9a08g045s33-pcie: Fix naming properties
  dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3E SoC
  PCI: rzg3s-host: Make SYSC register offsets SoC-specific
  PCI: rzg3s-host: Make configuration reset lines optional
  PCI: rzg3s-host: Add SoC-specific configuration and initialization
    callbacks
  PCI: rzg3s-host: Explicitly set class code for RZ/G3E compatibility
  PCI: rzg3s-host: Add PCIe Gen3 (8.0 GT/s) link speed support
  PCI: rzg3s-host: Add support for RZ/G3E PCIe controller
  arm64: dts: renesas: r9a09g047: Add PCIe node
  arm64: dts: renesas: r9a09g047e57-smarc-som: Add PCIe reference clock
  arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe

Thank you for the patches, Ive tested them on RZ/V2N EVK where PCIe IP
is identical to RZ/G3E.

Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> # RZ/V2N EVK

Cheers,
Prabhakar

 .../bindings/pci/renesas,r9a08g045-pcie.yaml  | 121 ++++--
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |  69 ++++
 .../boot/dts/renesas/r9a09g047e57-smarc.dts   |  16 +
 .../boot/dts/renesas/renesas-smarc2.dtsi      |   4 +
 .../boot/dts/renesas/rzg3e-smarc-som.dtsi     |  11 +
 drivers/clk/renesas/r9a09g047-cpg.c           |   5 +
 drivers/pci/controller/pcie-rzg3s-host.c      | 362 ++++++++++++++----
 7 files changed, 478 insertions(+), 110 deletions(-)

--
2.25.1