On Mon, Feb 16, 2026 at 12:00:39PM -0300, Marcelo Schmitt wrote:
AD4030 and similar ADCs can capture data at sample rates up to 2 mega
samples per second (MSPS). Not all SPI controllers are able to achieve such
high throughputs and even when the controller is fast enough to run
transfers at the required speed, it may be costly to the CPU to handle
transfer data at such high sample rates. Add SPI offload support for AD4030
and similar ADCs to enable data capture at maximum sample rates.
...
+ depends on PWM
Seeing this without being mentioned in the commit message is confusing.
Would be nice to add a sentence explaining that "The offload is initiated by
pulses from PWM..." (or in your own words, but make it clear).
...
+static int ad4030_set_sampling_freq(struct iio_dev *indio_dev, int freq_hz)
+{
+ struct ad4030_state *st = iio_priv(indio_dev);
+
+ if (!in_range(freq_hz, 1, st->chip->max_sample_rate_hz))
Hmm... Isn't it a off-by-one issue here (because the start == 1)?
Maybe
if (freq_hz == 0)
return -EINVAL;
if (!in_range(freq_hz, 0, st->chip->max_sample_rate_hz))
return -ERANGE;
+ return -EINVAL;
?
+ return ad4030_update_conversion_rate(st, freq_hz, st->avg_log2);
+}
--
With Best Regards,
Andy Shevchenko