[PATCH v4 19/20] arm64: dts: renesas: r9a09g047: Add DU{0,1} and DSI nodes
From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Date: 2026-02-02 12:01:11
Also in:
dri-devel, linux-clk, linux-renesas-soc, lkml
Subsystem:
arm/risc-v/renesas architecture, the rest · Maintainers:
Geert Uytterhoeven, Magnus Damm, Linus Torvalds
Add DU0, DU1, DSI nodes to RZ/RZG3E SoC DTSI. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> --- v1->v2: - Use single compatible string instead of multiple compatible strings for the two DU instances, leveraging a 'renesas,id' property to differentiate between DU0 and DU1. - Use vclk instead of vclk1 for DSI Node and set to the right position. v2->v3: - No changes. v3->v4: - No changes. arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 123 +++++++++++++++++++++ 1 file changed, 123 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index d4db44b6ccf7..46240a6ff992 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi@@ -1432,6 +1432,129 @@ csi2cru: endpoint@0 { }; }; + dsi: dsi@16430000 { + compatible = "renesas,r9a09g047-mipi-dsi"; + reg = <0 0x16430000 0 0x20000>; + interrupts = <GIC_SPI 874 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 876 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 877 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 878 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 879 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 880 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "seq0", "seq1", "vin1", "rcv", + "ferr", "ppi", "debug"; + clocks = <&cpg CPG_MOD 0xec>, <&cpg CPG_MOD 0xe9>, + <&cpg CPG_MOD 0xe8>, <&cpg CPG_MOD 0xea>, + <&cpg CPG_MOD 0x190>, <&cpg CPG_MOD 0xeb>; + clock-names = "pllrefclk", "aclk", "pclk", "vclk", + "lpclk", "vclk2"; + resets = <&cpg 0xd8>, <&cpg 0xd7>; + reset-names = "arst", "prst"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in0: endpoint { + }; + }; + + port@1 { + reg = <1>; + dsi_in1: endpoint { + }; + }; + + port@2 { + reg = <2>; + dsi_out: endpoint { + }; + }; + }; + }; + + du0: display@16460000 { + compatible = "renesas,r9a09g047-du"; + reg = <0 0x16460000 0 0x10000>; + interrupts = <GIC_SPI 882 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 0xed>, + <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg 0xdc>; + renesas,vsps = <&vspd0 0>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du0_out_dsi0: endpoint { + }; + }; + + port@1 { + reg = <1>; + du0_out_lvds0: endpoint { + }; + }; + + port@2 { + reg = <2>; + du0_out_lvds1: endpoint { + }; + }; + }; + }; + + du1: display@16490000 { + compatible = "renesas,r9a09g047-du"; + reg = <0 0x16490000 0 0x10000>; + interrupts = <GIC_SPI 922 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 0x1a8>, + <&cpg CPG_MOD 0x1a9>, + <&cpg CPG_MOD 0x1aa>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg 0x11e>; + renesas,vsps = <&vspd1 0>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du1_out_dsi0: endpoint { + }; + }; + + port@1 { + reg = <1>; + du1_out_lvds0: endpoint { + }; + }; + + port@3 { + reg = <3>; + du1_out_rgb0: endpoint { + }; + }; + + }; + }; + fcpvd0: fcp@16470000 { compatible = "renesas,r9a09g047-fcpvd", "renesas,fcpv";
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2.43.0