[PATCH v4 17/20] arm64: dts: renesas: r9a09g047: Add fcpvd{0,1} nodes
From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Date: 2026-02-02 12:00:56
Also in:
dri-devel, linux-clk, linux-renesas-soc, lkml
Subsystem:
arm/risc-v/renesas architecture, the rest · Maintainers:
Geert Uytterhoeven, Magnus Damm, Linus Torvalds
Add fcpvd{0,1} nodes to RZ/G3E SoC DTSI.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
v1->v2:
- Squashed fcpvd0 and fcpvd1 patches into a single patch.
- Collected tags.
v2->v3:
- No changes.
v3->v4:
- No changes.
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 24 ++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index cbb48ff5028f..c90a778250d6 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi@@ -1431,6 +1431,30 @@ csi2cru: endpoint@0 { }; }; }; + + fcpvd0: fcp@16470000 { + compatible = "renesas,r9a09g047-fcpvd", + "renesas,fcpv"; + reg = <0 0x16470000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xed>, + <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + resets = <&cpg 0xdc>; + power-domains = <&cpg>; + }; + + fcpvd1: fcp@164a0000 { + compatible = "renesas,r9a09g047-fcpvd", + "renesas,fcpv"; + reg = <0 0x164a0000 0 0x10000>; + clocks = <&cpg CPG_MOD 0x1a8>, + <&cpg CPG_MOD 0x1a9>, + <&cpg CPG_MOD 0x1aa>; + clock-names = "aclk", "pclk", "vclk"; + resets = <&cpg 0x11e>; + power-domains = <&cpg>; + }; }; stmmac_axi_setup: stmmac-axi-config {
--
2.43.0