Re: [PATCH v4 3/4] arm64: dts: qcom: Introduce Glymur base dtsi

Introduce the base device tree support for Glymur – Qualcomm's
next-generation compute SoC. The new glymur.dtsi describes the core SoC
components, including:

- CPUs and CPU topology
- Interrupt controller and TLMM
- GCC,DISPCC and RPMHCC clock controllers
- Reserved memory and interconnects
- APPS and PCIe SMMU and firmware SCM
- Watchdog, RPMHPD, APPS RSC and SRAM
- PSCI and PMU nodes
- QUPv3 serial engines
- CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS
- PDP0 mailbox, IPCC and AOSS
- Display clock controller
- SPMI PMIC arbiter with SPMI0/1/2 buses
- SMP2P nodes
- TSENS and thermal zones (8 instances, 92 sensors)

Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104,
PMH0110 along with temp-alarm and GPIO nodes needed on Glymur

Enabled PCIe controllers and associated PHY to support boot to
shell with nvme storage,
List of PCIe instances enabled:

- PCIe3b
- PCIe4
- PCIe5
- PCIe6

Co-developed-by: Jyothi Kumar Seerapu <redacted>
Signed-off-by: Jyothi Kumar Seerapu <redacted>
Co-developed-by: Maulik Shah <redacted>
Signed-off-by: Maulik Shah <redacted>
Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Co-developed-by: Taniya Das <redacted>
Signed-off-by: Taniya Das <redacted>
Co-developed-by: Kamal Wadhwa <redacted>
Signed-off-by: Kamal Wadhwa <redacted>
Co-developed-by: Qiang Yu <redacted>
Signed-off-by: Qiang Yu <redacted>
Co-developed-by: Abel Vesa <redacted>
Signed-off-by: Abel Vesa <redacted>
Co-developed-by: Manaf Meethalavalappu Pallikunhi <redacted>
Signed-off-by: Manaf Meethalavalappu Pallikunhi <redacted>
Co-developed-by: Jishnu Prakash <redacted>
Signed-off-by: Jishnu Prakash <redacted>
Signed-off-by: Pankaj Patil <redacted>
---
 arch/arm64/boot/dts/qcom/glymur.dtsi         | 5919 ++++++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/pmcx0102.dtsi       |  107 +
 arch/arm64/boot/dts/qcom/pmh0101.dtsi        |   45 +
 arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi |   83 +
 arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi |   83 +
 arch/arm64/boot/dts/qcom/pmk8850.dtsi        |   70 +
 arch/arm64/boot/dts/qcom/smb2370.dtsi        |   45 +
 7 files changed, 6352 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
new file mode 100644
index 000000000000..91e577bd152f
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi

@@ -0,0 +1,5919 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/clock/qcom,glymur-dispcc.h>
+#include <dt-bindings/clock/qcom,glymur-gcc.h>
+#include <dt-bindings/clock/qcom,glymur-tcsr.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/spmi/spmi.h>
+
+#include "glymur-ipcc.h"
+
+/ {
+	interrupt-parent = <&intc>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "qcom,oryon";