[PATCH v2 5/9] clk: realtek: Add support for gate clock
From: Yu-Chun Lin <eleanor.lin@realtek.com>
Date: 2026-01-13 11:23:55
Also in:
linux-clk, lkml
Subsystem:
common clk framework, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Linus Torvalds
From: Cheng-Yu Lee <redacted> Introduce clk_regmap_gate_ops supporting enable, disable, is_enabled, and disable_unused for standard regmap gate clocks. Add clk_regmap_gate_ro_ops as a read-only variant exposing only is_enabled. Signed-off-by: Cheng-Yu Lee <redacted> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> --- Changes in v2: - Added missing Co-developed-by tag. - Added error handling for regmap_update_bits. - Removed .disable_unused callback in gate ops. The CCF handles the fallback to .disable automatically if .disable_unused is not present. --- drivers/clk/realtek/Makefile | 2 + drivers/clk/realtek/clk-regmap-gate.c | 66 +++++++++++++++++++++++++++ drivers/clk/realtek/clk-regmap-gate.h | 65 ++++++++++++++++++++++++++ 3 files changed, 133 insertions(+) create mode 100644 drivers/clk/realtek/clk-regmap-gate.c create mode 100644 drivers/clk/realtek/clk-regmap-gate.h
diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile
index c173ea3b10e3..97058d48a176 100644
--- a/drivers/clk/realtek/Makefile
+++ b/drivers/clk/realtek/Makefile@@ -2,6 +2,8 @@ obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o clk-rtk-y += common.o + clk-rtk-y += clk-pll.o +clk-rtk-y += clk-regmap-gate.o clk-rtk-y += freq_table.o clk-rtk-y += reset.o
diff --git a/drivers/clk/realtek/clk-regmap-gate.c b/drivers/clk/realtek/clk-regmap-gate.c
new file mode 100644
index 000000000000..5d0c402993d9
--- /dev/null
+++ b/drivers/clk/realtek/clk-regmap-gate.c@@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee <cylee12@realtek.com> + */ + +#include "clk-regmap-gate.h" + +static int clk_regmap_gate_enable(struct clk_hw *hw) +{ + struct clk_regmap_gate *clkg = to_clk_regmap_gate(hw); + unsigned int mask; + unsigned int val; + + mask = BIT(clkg->bit_idx); + val = BIT(clkg->bit_idx); + + if (clkg->write_en) { + mask |= BIT(clkg->bit_idx + 1); + val |= BIT(clkg->bit_idx + 1); + } + + return regmap_update_bits(clkg->clkr.regmap, clkg->gate_ofs, mask, val); +} + +static void clk_regmap_gate_disable(struct clk_hw *hw) +{ + struct clk_regmap_gate *clkg = to_clk_regmap_gate(hw); + unsigned int mask; + unsigned int val; + + mask = BIT(clkg->bit_idx); + val = 0; + + if (clkg->write_en) { + mask |= BIT(clkg->bit_idx + 1); + val |= BIT(clkg->bit_idx + 1); + } + + regmap_update_bits(clkg->clkr.regmap, clkg->gate_ofs, mask, val); +} + +static int clk_regmap_gate_is_enabled(struct clk_hw *hw) +{ + struct clk_regmap_gate *clkg = to_clk_regmap_gate(hw); + int ret; + u32 val; + + ret = regmap_read(clkg->clkr.regmap, clkg->gate_ofs, &val); + if (ret < 0) + return ret; + + return !!(val & BIT(clkg->bit_idx)); +} + +const struct clk_ops clk_regmap_gate_ops = { + .enable = clk_regmap_gate_enable, + .disable = clk_regmap_gate_disable, + .is_enabled = clk_regmap_gate_is_enabled, +}; +EXPORT_SYMBOL_GPL(clk_regmap_gate_ops); + +const struct clk_ops clk_regmap_gate_ro_ops = { + .is_enabled = clk_regmap_gate_is_enabled, +}; +EXPORT_SYMBOL_GPL(clk_regmap_gate_ro_ops);
diff --git a/drivers/clk/realtek/clk-regmap-gate.h b/drivers/clk/realtek/clk-regmap-gate.h
new file mode 100644
index 000000000000..41cbe27865a7
--- /dev/null
+++ b/drivers/clk/realtek/clk-regmap-gate.h@@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee <cylee12@realtek.com> + */ + +#ifndef __CLK_REALTEK_CLK_REGMAP_GATE_H +#define __CLK_REALTEK_CLK_REGMAP_GATE_H + +#include "common.h" + +struct clk_regmap_gate { + struct clk_regmap clkr; + int gate_ofs; + u8 bit_idx; + u32 write_en : 1; +}; + +#define __clk_regmap_gate_hw(_p) __clk_regmap_hw(&(_p)->clkr) + +#define __CLK_REGMAP_GATE(_name, _parent, _ops, _flags, _ofs, _bit_idx, \ + _write_en) \ + struct clk_regmap_gate _name = { \ + .clkr.hw.init = CLK_HW_INIT(#_name, _parent, _ops, _flags), \ + .gate_ofs = _ofs, \ + .bit_idx = _bit_idx, \ + .write_en = _write_en, \ + } + +#define CLK_REGMAP_GATE(_name, _parent, _flags, _ofs, _bit_idx, _write_en) \ + __CLK_REGMAP_GATE(_name, _parent, &clk_regmap_gate_ops, _flags, _ofs, \ + _bit_idx, _write_en) + +#define CLK_REGMAP_GATE_RO(_name, _parent, _flags, _ofs, _bit_idx, _write_en) \ + __CLK_REGMAP_GATE(_name, _parent, &clk_regmap_gate_ro_ops, _flags, \ + _ofs, _bit_idx, _write_en) + +#define __CLK_REGMAP_GATE_NO_PARENT(_name, _ops, _flags, _ofs, _bit_idx, \ + _write_en) \ + struct clk_regmap_gate _name = { \ + .clkr.hw.init = CLK_HW_INIT_NO_PARENT(#_name, _ops, _flags), \ + .gate_ofs = _ofs, \ + .bit_idx = _bit_idx, \ + .write_en = _write_en, \ + } + +#define CLK_REGMAP_GATE_NO_PARENT(_name, _flags, _ofs, _bit_idx, _write_en) \ + __CLK_REGMAP_GATE_NO_PARENT(_name, &clk_regmap_gate_ops, _flags, _ofs, \ + _bit_idx, _write_en) + +#define CLK_REGMAP_GATE_NO_PARENT_RO(_name, _flags, _ofs, _bit_idx, _write_en) \ + __CLK_REGMAP_GATE_NO_PARENT(_name, &clk_regmap_gate_ro_ops, _flags, \ + _ofs, _bit_idx, _write_en) + +static inline struct clk_regmap_gate *to_clk_regmap_gate(struct clk_hw *hw) +{ + struct clk_regmap *clkr = to_clk_regmap(hw); + + return container_of(clkr, struct clk_regmap_gate, clkr); +} + +extern const struct clk_ops clk_regmap_gate_ops; +extern const struct clk_ops clk_regmap_gate_ro_ops; + +#endif /* __CLK_REALTEK_CLK_REGMAP_GATE_H */
--
2.34.1