[PATCH v2 4/9] clk: realtek: Add support for phase locked loops (PLLs)
From: Yu-Chun Lin <eleanor.lin@realtek.com>
Date: 2026-01-13 11:23:55
Also in:
linux-clk, lkml
Subsystem:
common clk framework, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Linus Torvalds
From: Cheng-Yu Lee <redacted> Provide a full set of PLL operations for programmable PLLs and a read-only variant for fixed or hardware-managed PLLs. Signed-off-by: Cheng-Yu Lee <redacted> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> --- Changes in v2: - Added missing Co-developed-by tag. - Fixed clk_pll_determine_rate() to properly update req->rate. - Removed the redundant .disable_unused callback. --- drivers/clk/realtek/Makefile | 2 + drivers/clk/realtek/clk-pll.c | 189 +++++++++++++++++++++++++++++++ drivers/clk/realtek/clk-pll.h | 47 ++++++++ drivers/clk/realtek/freq_table.c | 35 ++++++ drivers/clk/realtek/freq_table.h | 23 ++++ 5 files changed, 296 insertions(+) create mode 100644 drivers/clk/realtek/clk-pll.c create mode 100644 drivers/clk/realtek/clk-pll.h create mode 100644 drivers/clk/realtek/freq_table.c create mode 100644 drivers/clk/realtek/freq_table.h
diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile
index 4041951b7c62..c173ea3b10e3 100644
--- a/drivers/clk/realtek/Makefile
+++ b/drivers/clk/realtek/Makefile@@ -2,4 +2,6 @@ obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o clk-rtk-y += common.o +clk-rtk-y += clk-pll.o +clk-rtk-y += freq_table.o clk-rtk-y += reset.o
diff --git a/drivers/clk/realtek/clk-pll.c b/drivers/clk/realtek/clk-pll.c
new file mode 100644
index 000000000000..a3fd1fffbc92
--- /dev/null
+++ b/drivers/clk/realtek/clk-pll.c@@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee <cylee12@realtek.com> + */ + +#include "clk-pll.h" + +#define TIMEOUT 2000 + +static int wait_freq_ready(struct clk_pll *clkp) +{ + u32 pollval; + + if (!clkp->freq_ready_valid) + return 0; + + return regmap_read_poll_timeout_atomic(clkp->clkr.regmap, clkp->freq_ready_reg, pollval, + (pollval & clkp->freq_ready_mask) == clkp->freq_ready_val, + 0, TIMEOUT); +} + +static bool is_power_on(struct clk_pll *clkp) +{ + u32 val; + int ret; + + if (!clkp->power_reg) + return true; + + ret = regmap_read(clkp->clkr.regmap, clkp->power_reg, &val); + if (ret) + return true; + + return (val & clkp->power_mask) == clkp->power_val_on; +} + +static int get_freq_val_raw(struct clk_pll *clkp, u32 *val) +{ + int ret; + + ret = regmap_read(clkp->clkr.regmap, clkp->freq_reg, val); + if (ret) + return ret; + + return 0; +} + +static int get_freq_val(struct clk_pll *clkp, u32 *val) +{ + int ret; + u32 raw_val; + + ret = get_freq_val_raw(clkp, &raw_val); + if (ret) + return ret; + + *val = raw_val & clkp->freq_mask; + return 0; +} + +static void clk_pll_disable(struct clk_hw *hw) +{ + struct clk_pll *clkp = to_clk_pll(hw); + + if (!clkp->seq_power_off) + return; + + regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_power_off, + clkp->num_seq_power_off); +} + +static int clk_pll_is_enabled(struct clk_hw *hw) +{ + struct clk_pll *clkp = to_clk_pll(hw); + + return is_power_on(clkp); +} + +static int clk_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_pll *clkp = to_clk_pll(hw); + const struct freq_table *ftblv = NULL; + + ftblv = ftbl_find_by_rate(clkp->freq_tbl, req->rate); + if (!ftblv) + return -EINVAL; + + req->rate = ftblv->rate; + return 0; +} + +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_pll *clkp = to_clk_pll(hw); + const struct freq_table *fv; + u32 freq_val; + int ret; + + ret = get_freq_val(clkp, &freq_val); + if (ret) + return 0; + + fv = ftbl_find_by_val_with_mask(clkp->freq_tbl, clkp->freq_mask, + freq_val); + return fv ? fv->rate : 0; +} + +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_pll *clkp = to_clk_pll(hw); + const struct freq_table *fv; + u32 freq_val; + int ret; + + fv = ftbl_find_by_rate(clkp->freq_tbl, rate); + if (!fv || fv->rate != rate) + return -EINVAL; + + ret = get_freq_val_raw(clkp, &freq_val); + if (ret) + return ret; + + freq_val &= ~clkp->freq_mask; + freq_val |= (fv->val & clkp->freq_mask); + + if (clkp->seq_pre_set_freq) { + ret = regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_pre_set_freq, + clkp->num_seq_pre_set_freq); + if (ret) + return ret; + } + + ret = regmap_write(clkp->clkr.regmap, clkp->freq_reg, freq_val); + if (ret) + return ret; + + if (clkp->seq_post_set_freq) { + ret = regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_post_set_freq, + clkp->num_seq_post_set_freq); + if (ret) + return ret; + } + + if (is_power_on(clkp)) { + ret = wait_freq_ready(clkp); + if (ret) + return ret; + } + + return 0; +} + +static int clk_pll_enable(struct clk_hw *hw) +{ + struct clk_pll *clkp = to_clk_pll(hw); + int ret; + + if (!clkp->seq_power_on) + return 0; + + if (is_power_on(clkp)) + return 0; + + ret = regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_power_on, + clkp->num_seq_power_on); + if (ret) + return ret; + + return wait_freq_ready(clkp); +} + +const struct clk_ops clk_pll_ops = { + .enable = clk_pll_enable, + .disable = clk_pll_disable, + .is_enabled = clk_pll_is_enabled, + .recalc_rate = clk_pll_recalc_rate, + .determine_rate = clk_pll_determine_rate, + .set_rate = clk_pll_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_pll_ops); + +const struct clk_ops clk_pll_ro_ops = { + .recalc_rate = clk_pll_recalc_rate, +}; +EXPORT_SYMBOL_GPL(clk_pll_ro_ops);
diff --git a/drivers/clk/realtek/clk-pll.h b/drivers/clk/realtek/clk-pll.h
new file mode 100644
index 000000000000..c3e2e5ca641f
--- /dev/null
+++ b/drivers/clk/realtek/clk-pll.h@@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017-2019 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee <cylee12@realtek.com> + */ + +#ifndef __CLK_REALTEK_CLK_PLL_H +#define __CLK_REALTEK_CLK_PLL_H + +#include "common.h" +#include "freq_table.h" + +struct clk_pll { + struct clk_regmap clkr; + const struct reg_sequence *seq_power_on; + u32 num_seq_power_on; + const struct reg_sequence *seq_power_off; + u32 num_seq_power_off; + const struct reg_sequence *seq_pre_set_freq; + u32 num_seq_pre_set_freq; + const struct reg_sequence *seq_post_set_freq; + u32 num_seq_post_set_freq; + const struct freq_table *freq_tbl; + u32 freq_reg; + u32 freq_mask; + u32 freq_ready_valid; + u32 freq_ready_mask; + u32 freq_ready_reg; + u32 freq_ready_val; + u32 power_reg; + u32 power_mask; + u32 power_val_on; +}; + +#define __clk_pll_hw(_ptr) __clk_regmap_hw(&(_ptr)->clkr) + +static inline struct clk_pll *to_clk_pll(struct clk_hw *hw) +{ + struct clk_regmap *clkr = to_clk_regmap(hw); + + return container_of(clkr, struct clk_pll, clkr); +} + +extern const struct clk_ops clk_pll_ops; +extern const struct clk_ops clk_pll_ro_ops; + +#endif /* __CLK_REALTEK_CLK_PLL_H */
diff --git a/drivers/clk/realtek/freq_table.c b/drivers/clk/realtek/freq_table.c
new file mode 100644
index 000000000000..26a0d2d3e851
--- /dev/null
+++ b/drivers/clk/realtek/freq_table.c@@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "freq_table.h" + +const struct freq_table *ftbl_find_by_rate(const struct freq_table *ftbl, + unsigned long rate) +{ + unsigned long best_rate = 0; + const struct freq_table *best = NULL; + + for (; !IS_FREQ_TABLE_END(ftbl); ftbl++) { + if (ftbl->rate == rate) + return ftbl; + + if (ftbl->rate > rate) + continue; + + if (ftbl->rate > best_rate) { + best_rate = ftbl->rate; + best = ftbl; + } + } + + return best; +} + +const struct freq_table * +ftbl_find_by_val_with_mask(const struct freq_table *ftbl, u32 mask, u32 value) +{ + for (; !IS_FREQ_TABLE_END(ftbl); ftbl++) { + if ((ftbl->val & mask) == (value & mask)) + return ftbl; + } + return NULL; +};
diff --git a/drivers/clk/realtek/freq_table.h b/drivers/clk/realtek/freq_table.h
new file mode 100644
index 000000000000..66a0b0610e38
--- /dev/null
+++ b/drivers/clk/realtek/freq_table.h@@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <linux/bitops.h> + +struct freq_table { + u32 val; + unsigned long rate; +}; + +/* ofs check */ +#define CLK_OFS_INVALID (-1) +#define CLK_OFS_IS_VALID(_ofs) ((_ofs) != CLK_OFS_INVALID) + +#define FREQ_TABLE_END \ + { \ + .rate = 0 \ + } +#define IS_FREQ_TABLE_END(_f) ((_f)->rate == 0) + +const struct freq_table *ftbl_find_by_rate(const struct freq_table *ftbl, + unsigned long rate); +const struct freq_table * +ftbl_find_by_val_with_mask(const struct freq_table *ftbl, u32 mask, u32 value);
--
2.34.1