[PATCH 4/9] clk: qcom: rpmh: Add support for Kaanapali rpmh clocks
From: Jingyi Wang <hidden>
Date: 2025-09-24 22:59:09
Also in:
linux-arm-msm, linux-clk, lkml
Subsystem:
arm/qualcomm mailing list, common clk framework, qualcomm clock drivers, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Bjorn Andersson, Linus Torvalds
From: Taniya Das <redacted> Add the RPMH clocks present in Kaanapali SoC. Signed-off-by: Taniya Das <redacted> Signed-off-by: Jingyi Wang <redacted> --- drivers/clk/qcom/clk-rpmh.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index 63c38cb47bc4..6b1f24ee66d5 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c@@ -395,6 +395,16 @@ DEFINE_CLK_RPMH_VRM(clk4, _a, "C4A_E0", 1); DEFINE_CLK_RPMH_VRM(clk5, _a, "C5A_E0", 1); DEFINE_CLK_RPMH_VRM(clk8, _a, "C8A_E0", 1); +DEFINE_CLK_RPMH_VRM(c1a_e0, _a, "C1A_E0", 1); +DEFINE_CLK_RPMH_VRM(c2a_e0, _a, "C2A_E0", 1); +DEFINE_CLK_RPMH_VRM(c3a_e0, _a2, "C3A_E0", 2); +DEFINE_CLK_RPMH_VRM(c4a_e0, _a2, "C4A_E0", 2); +DEFINE_CLK_RPMH_VRM(c5a_e0, _a2, "C5A_E0", 2); +DEFINE_CLK_RPMH_VRM(c6a_e0, _a2, "C6A_E0", 2); +DEFINE_CLK_RPMH_VRM(c7a_e0, _a2, "C7A_E0", 2); +DEFINE_CLK_RPMH_VRM(c8a_e0, _a2, "C8A_E0", 2); +DEFINE_CLK_RPMH_VRM(c11a_e0, _a4, "C11A_E0", 4); + DEFINE_CLK_RPMH_BCM(ce, "CE0"); DEFINE_CLK_RPMH_BCM(hwkm, "HK0"); DEFINE_CLK_RPMH_BCM(ipa, "IP0");
@@ -900,6 +910,34 @@ static const struct clk_rpmh_desc clk_rpmh_glymur = { .num_clks = ARRAY_SIZE(glymur_rpmh_clocks), }; +static struct clk_hw *kaanapali_rpmh_clocks[] = { + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, + [RPMH_DIV_CLK1] = &clk_rpmh_c11a_e0_a4.hw, + [RPMH_LN_BB_CLK1] = &clk_rpmh_c6a_e0_a2.hw, + [RPMH_LN_BB_CLK1_A] = &clk_rpmh_c6a_e0_a2_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_c7a_e0_a2.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_c7a_e0_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &clk_rpmh_c8a_e0_a2.hw, + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_c8a_e0_a2_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_c1a_e0_a.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_c1a_e0_a_ao.hw, + [RPMH_RF_CLK2] = &clk_rpmh_c2a_e0_a.hw, + [RPMH_RF_CLK2_A] = &clk_rpmh_c2a_e0_a_ao.hw, + [RPMH_RF_CLK3] = &clk_rpmh_c3a_e0_a2.hw, + [RPMH_RF_CLK3_A] = &clk_rpmh_c3a_e0_a2_ao.hw, + [RPMH_RF_CLK4] = &clk_rpmh_c4a_e0_a2.hw, + [RPMH_RF_CLK4] = &clk_rpmh_c4a_e0_a2.hw, + [RPMH_RF_CLK5_A] = &clk_rpmh_c5a_e0_a2_ao.hw, + [RPMH_RF_CLK5_A] = &clk_rpmh_c5a_e0_a2_ao.hw, + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_kaanapali = { + .clks = kaanapali_rpmh_clocks, + .num_clks = ARRAY_SIZE(kaanapali_rpmh_clocks), +}; + static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, void *data) {
@@ -990,6 +1028,7 @@ static int clk_rpmh_probe(struct platform_device *pdev) static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,glymur-rpmh-clk", .data = &clk_rpmh_glymur}, + { .compatible = "qcom,kaanapali-rpmh-clk", .data = &clk_rpmh_kaanapali}, { .compatible = "qcom,milos-rpmh-clk", .data = &clk_rpmh_milos}, { .compatible = "qcom,qcs615-rpmh-clk", .data = &clk_rpmh_qcs615}, { .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000},
--
2.25.1