On Wed, Sep 03, 2025 at 05:50:00PM +0200, Konrad Dybcio wrote:
On 9/3/25 1:47 PM, Wasim Nazir wrote:
quoted
From: Sushrut Shree Trivedi <redacted>
Enable PCIe0 and PCIe1 along with the respective phy-nodes.
PCIe0 is routed to an m.2 E key connector on the mainboard for wifi
attaches while PCIe1 routes to a standard PCIe x4 expansion slot.
Signed-off-by: Sushrut Shree Trivedi <redacted>
Signed-off-by: Wasim Nazir <redacted>
---
arch/arm64/boot/dts/qcom/lemans-evk.dts | 82 +++++++++++++++++++++++++++++++++
1 file changed, 82 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts
index 196c5ee0dd34..7528fa1c661a 100644
--- a/arch/arm64/boot/dts/qcom/lemans-evk.dts
+++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts
@@ -379,6 +379,40 @@ &mdss0_dp1_phy {
status = "okay";
};
+&pcie0 {
+ perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_default_state>;
property-n
property-names
in this order, please
Ack.
Konrad
--
Regards,
Wasim