[PATCH v3 02/10] dt-bindings: clock: mediatek: Document #access-controller-cells
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Date: 2025-08-05 07:48:39
Also in:
linux-arm-kernel, linux-mediatek, linux-pm, lkml
Subsystem:
common clk framework, open firmware and flattened device tree bindings, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Allow the #access-controller-cells property on all of the infracfg controllers on all MediaTek SoCs, as this always acts as an access control provider. Reviewed-by: Nícolas F. R. A. Prado <redacted> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- .../bindings/clock/mediatek,infracfg.yaml | 3 +++ .../bindings/clock/mediatek,mt8186-sys-clock.yaml | 15 +++++++++++++++ .../bindings/clock/mediatek,mt8188-sys-clock.yaml | 15 +++++++++++++++ .../bindings/clock/mediatek,mt8192-sys-clock.yaml | 15 +++++++++++++++ .../bindings/clock/mediatek,mt8195-sys-clock.yaml | 15 +++++++++++++++ .../bindings/clock/mediatek,mt8365-sys-clock.yaml | 15 +++++++++++++++ 6 files changed, 78 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml b/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml
index d1d30700d9b0..27f1a31c3424 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml@@ -47,6 +47,9 @@ properties: reg: maxItems: 1 + '#access-controller-cells': + const: 0 + '#clock-cells': const: 1
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
index 1c446fbc5108..2a1bf9073b7d 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml@@ -36,6 +36,9 @@ properties: reg: maxItems: 1 + '#access-controller-cells': + const: 0 + '#clock-cells': const: 1
@@ -48,6 +51,18 @@ required: additionalProperties: false +if: + properties: + compatible: + contains: + const: mediatek,mt8186-infracfg_ao +then: + properties: + '#access-controller-cells': true +else: + properties: + '#access-controller-cells': false + examples: - | topckgen: syscon@10000000 {
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml
index db13d51a4903..08472d363e8a 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml@@ -36,6 +36,9 @@ properties: reg: maxItems: 1 + '#access-controller-cells': + const: 0 + '#clock-cells': const: 1
@@ -49,6 +52,18 @@ required: additionalProperties: false +if: + properties: + compatible: + contains: + const: mediatek,mt8188-infracfg_ao +then: + properties: + '#access-controller-cells': true +else: + properties: + '#access-controller-cells': false + examples: - | clock-controller@10000000 {
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-clock.yaml
index bf8c9aacdf1e..f1ab8b0e0a98 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-clock.yaml@@ -26,6 +26,9 @@ properties: reg: maxItems: 1 + '#access-controller-cells': + const: 0 + '#clock-cells': const: 1
@@ -38,6 +41,18 @@ required: additionalProperties: false +if: + properties: + compatible: + contains: + const: mediatek,mt8192-infracfg +then: + properties: + '#access-controller-cells': true +else: + properties: + '#access-controller-cells': false + examples: - | topckgen: syscon@10000000 {
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-clock.yaml
index 69f096eb168d..dcce8b188e4f 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-clock.yaml@@ -34,6 +34,9 @@ properties: reg: maxItems: 1 + '#access-controller-cells': + const: 0 + '#clock-cells': const: 1
@@ -46,6 +49,18 @@ required: additionalProperties: false +if: + properties: + compatible: + contains: + const: mediatek,mt8195-infracfg_ao +then: + properties: + '#access-controller-cells': true +else: + properties: + '#access-controller-cells': false + examples: - | topckgen: syscon@10000000 {
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml
index 643f84660c8e..b6f074f98db7 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml@@ -28,6 +28,9 @@ properties: reg: maxItems: 1 + '#access-controller-cells': + const: 0 + '#clock-cells': const: 1
@@ -38,6 +41,18 @@ required: additionalProperties: false +if: + properties: + compatible: + contains: + const: mediatek,mt8365-infracfg +then: + properties: + '#access-controller-cells': true +else: + properties: + '#access-controller-cells': false + examples: - | topckgen: clock-controller@10000000 {
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2.50.1