[PATCH v1 2/4] dt-bindings: PCI: qcom,pcie-sa8775p: document link_down reset
From: Ziyue Zhang <hidden>
Date: 2025-05-29 03:54:33
Also in:
linux-arm-msm, linux-pci, linux-phy, lkml
Subsystem:
arm/qualcomm mailing list, open firmware and flattened device tree bindings, pci native host bridge and endpoint drivers, pci subsystem, the rest · Maintainers:
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas, Linus Torvalds
Each PCIe controller on sa8775p supports 'link_down'reset on hardware, document it. Signed-off-by: Ziyue Zhang <redacted> --- .../devicetree/bindings/pci/qcom,pcie-sa8775p.yaml | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
index e3fa232da2ca..805258cbcf2f 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml@@ -61,11 +61,14 @@ properties: - const: global resets: - maxItems: 1 + minItems: 1 + maxItems: 2 reset-names: + minItems: 1 items: - - const: pci + - const: pci # PCIe core reset + - const: link_down # PCIe link down reset required: - interconnects
@@ -161,8 +164,10 @@ examples: power-domains = <&gcc PCIE_0_GDSC>; - resets = <&gcc GCC_PCIE_0_BCR>; - reset-names = "pci"; + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
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2.34.1