[PATCH 6/9] arm64: dts: apple: t8010: Add CPU caches
From: Nick Chan <hidden>
Date: 2025-02-20 12:22:43
Also in:
asahi, linux-arm-kernel, lkml
Subsystem:
arm/apple machine support, the rest · Maintainers:
Sven Peter, Janne Grunau, Linus Torvalds
Add information about CPU caches in the P-cluster of Apple A10 SoC. Due to "Apple Fusion Architecture" big.LITTLE switcher, only caches from one of the clusters can be used at any given moment. Signed-off-by: Nick Chan <redacted> --- arch/arm64/boot/dts/apple/t8010.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/apple/t8010.dtsi b/arch/arm64/boot/dts/apple/t8010.dtsi
index b355d443ee476e7c98b352470e3b1b5d0fae7652..5d24da52cf255b6ad211d2ac40aad75a6194d595 100644
--- a/arch/arm64/boot/dts/apple/t8010.dtsi
+++ b/arch/arm64/boot/dts/apple/t8010.dtsi@@ -36,6 +36,9 @@ cpu0: cpu@0 { performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; /* P-core */ + d-cache-size = <0x10000>; /* P-core */ }; cpu1: cpu@1 {
@@ -46,6 +49,16 @@ cpu1: cpu@1 { performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; /* P-core */ + d-cache-size = <0x10000>; /* P-core */ + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x300000>; /* P-cluster */ }; };
--
2.48.1