[PATCH 1/9] arm64: dts: apple: s5l8960x: Add CPU caches
From: Nick Chan <hidden>
Date: 2025-02-20 12:22:29
Also in:
asahi, linux-arm-kernel, lkml
Subsystem:
arm/apple machine support, the rest · Maintainers:
Sven Peter, Janne Grunau, Linus Torvalds
Add information about CPU caches in Apple A7 SoC. Signed-off-by: Nick Chan <redacted> --- arch/arm64/boot/dts/apple/s5l8960x.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/apple/s5l8960x.dtsi b/arch/arm64/boot/dts/apple/s5l8960x.dtsi
index 64dbae5c73515bb6a1651b9b26d349d0cfd0408a..e58a3a280abf72c0a390cbefb4fdf89942d77512 100644
--- a/arch/arm64/boot/dts/apple/s5l8960x.dtsi
+++ b/arch/arm64/boot/dts/apple/s5l8960x.dtsi@@ -37,6 +37,9 @@ cpu0: cpu@0 { performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; }; cpu1: cpu@1 {
@@ -47,6 +50,16 @@ cpu1: cpu@1 { performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x100000>; }; };
--
2.48.1