RE: [PATCH v4 4/9] soc: renesas: rz-sysc: Add support for RZ/G3E family

-----Original Message-----
From: Geert Uytterhoeven <geert@linux-m68k.org>
Sent: Friday, January 24, 2025 3:20 PM
Subject: Re: [PATCH v4 4/9] soc: renesas: rz-sysc: Add support for RZ/G3E
family

Hi Geert,

Thanks for your review.

Hi John,

On Thu, Jan 23, 2025 at 6:05 PM John Madieu
[off-list ref] wrote:

quoted

Add SoC detection support for RZ/G3E SoC. Also add support for
detecting the number of cores and ETHOS-U55 NPU and also detect PLL
mismatch for SW settings other than 1.7GHz.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
v3 -> v4: No changes

Changes in v3:
- Removed Syscon support

Changes in v2:
- Group bitfields ordered by registers
- Rename SoC-specific callback field to 'print_id'
- Explicitely select 'MFD_SYSCON' config option
- Do not rely on 'syscon'-compatible probing anymore.

Thanks for the update!

quoted

--- /dev/null
+++ b/drivers/soc/renesas/r9a09g047-sys.c

@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/G3E System controller (SYS) driver
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#include <linux/bits.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include "rz-sysc.h"
+
+/* Register Offsets */
+#define SYS_LSI_MODE           0x300
+/*
+ * BOOTPLLCA[1:0]
+ *         [0,0] => 1.1GHZ
+ *         [0,1] => 1.5GHZ
+ *         [1,0] => 1.6GHZ
+ *         [1,1] => 1.7GHZ
+ */
+#define SYS_LSI_MODE_STAT_BOOTPLLCA55  GENMASK(12, 11)
+#define SYS_LSI_MODE_CA55_1_7GHZ       0x3

Please add a blank line here.

Will do, in v5.

quoted

+#define SYS_LSI_DEVID          0x304
+#define SYS_LSI_DEVID_REV      GENMASK(31, 28)
+#define SYS_LSI_DEVID_SPECIFIC GENMASK(27, 0)

Please align the second column in the three lines above.
Please add a blank line here.

quoted

+#define SYS_LSI_PRR                    0x308
+#define SYS_LSI_PRR_CA55_DIS           BIT(8)
+
+       dev_info(dev, "Detected Renesas %s Core %s %s Rev %s%s\n",
+                is_quad_core ? "Quad" : "Dual",
+                soc_dev_attr->family,

Fits on a single line.

quoted

+                soc_dev_attr->soc_id,
+                soc_dev_attr->revision,

Likewise.

They'll all be fixed in v5.

quoted

+                npu_enabled ? " with Ethos-U55" : "");
+
+       /* Check CA55 PLL configuration */
+       if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) !=

SYS_LSI_MODE_CA55_1_7GHZ)

quoted

+               dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n"); }

Gr{oetje,eeting}s,

                        Geert

Regards,
John