Hi Biju,

On Tue, Jan 14, 2025 at 9:55 AM Biju Das [off-list ref] wrote:

Hi Prabhakar,

Thanks for the patch.

quoted

-----Original Message-----
From: Prabhakar <prabhakar.csengg@gmail.com>
Sent: 13 January 2025 11:24
Subject: [PATCH v3 5/6] watchdog: rzv2h_wdt: Add support to retrieve the bootstatus information

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

On the RZ/V2H(P) SoC we can determine if the current boot is due to `Power-on-Reset` or due to the
`Watchdog`. The information used to determine this is present on the CPG block.

The CPG_ERROR_RSTm(m = 2 - 8) registers are set in response to an error interrupt causing an reset.
CPG_ERROR_RST2[ERROR_RST0/1/2] is set if there was an underflow/overflow on WDT1 causing an error
interrupt.

To fetch this information from CPG block `syscon` is used and bootstatus field in the watchdog device
is updated based on the CPG_ERROR_RST2[ERROR_RST0/1/2] bit. Upon consumig
CPG_ERROR_RST2[ERROR_RST0/1/2] bit we clear it.

As syscon-cpg is available, can we get rid of Linux assuming TF_A/U-boot for configuring Error Reset
Select Registers(0x10420B04)for the watchdog to reset the system?

Agreed.

After this, each watchdog device node will have, selection{offset,bit} status{ offset,bit}
renesas,syscon-cpg-error-rst-sel = <&cpg 0xb04 1>;
renesas,syscon-cpg-error-rst = <&cpg 0xb40 1>;

Or

renesas,syscon-cpg-error-rst = < &cpg 0xb04 1 0xb40 1>;

As we already have 0xb40 we can do 0xb40 - 0x3c to get `0xb04` in the
WDT driver and the same bit numbers can be re-used for
CPG_ERRORRST_SEL2,  so by this way we can avoid adding another
property in DT. And I think this works for G3E too?

Cheers,
Prabhakar