IPQ95xx SoCs have different OPPs available for the CPU based on
the SoC variant. This can be determined from an eFuse register
present in the silicon.

Added support for ipq95xx on nvmem driver which helps to
determine OPPs at runtime based on the eFuse register which
has the CPU frequency limits. opp-supported-hw dt binding
can be used to indicate the available OPPs for each limit.

Signed-off-by: Praveenkumar I <redacted>
Signed-off-by: Kathiravan T <redacted>
Signed-off-by: Varadarajan Narayanan <redacted>
---
 drivers/cpufreq/cpufreq-dt-platdev.c |  1 +
 drivers/cpufreq/qcom-cpufreq-nvmem.c | 20 ++++++++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index f0c45d4..4ab29c0 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c

@@ -180,6 +180,7 @@ static const struct of_device_id blocklist[] __initconst = {

        { .compatible = "qcom,ipq5332", },
        { .compatible = "qcom,ipq8064", },
+       { .compatible = "qcom,ipq9574", },
        { .compatible = "qcom,apq8064", },
        { .compatible = "qcom,msm8974", },
        { .compatible = "qcom,msm8960", },

diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 49d21b0..de70225 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c

@@ -168,6 +168,25 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
        case QCOM_ID_APQ8096SG:
                drv->versions = 1 << ((unsigned int)(*speedbin) + 4);
                break;
+       case QCOM_ID_IPQ9514:
+       case QCOM_ID_IPQ9550:
+       case QCOM_ID_IPQ9554:
+       case QCOM_ID_IPQ9570:
+       case QCOM_ID_IPQ9574:
+               /* Fuse Value    Freq    BIT to set
+                * ---------------------------------
+                *   2’b00     No Limit     BIT(0)
+                *   2’b10     1.8 GHz      BIT(1)
+                *   2’b01     1.5 Ghz      BIT(2)
+                *   2’b11     1.2 GHz      BIT(3)
+                */
+               if ((unsigned int)(*speedbin) == 2)
+                       drv->versions = BIT(1);
+               else if ((unsigned int)(*speedbin) == 1)
+                       drv->versions = BIT(2);
+               else
+                       drv->versions = 1 << (unsigned int)(*speedbin);

+               break;
        default:
                BUG();
                break;

@@ -375,6 +394,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
        { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
        { .compatible = "qcom,ipq5332", .data = &match_data_kryo },
        { .compatible = "qcom,ipq8064", .data = &match_data_krait },
+       { .compatible = "qcom,ipq9574", .data = &match_data_kryo },
        { .compatible = "qcom,apq8064", .data = &match_data_krait },
        { .compatible = "qcom,msm8974", .data = &match_data_krait },
        { .compatible = "qcom,msm8960", .data = &match_data_krait },
--

2.7.4