Hi Rob, 

On Tue, 2022-08-30 at 15:36 -0500, Rob Herring wrote:

On Thu, Aug 25, 2022 at 04:13:29PM +0200, Johannes Zink wrote:

quoted

This patch introduces additional memory areas of the machxo2-slave
fpga
to be erased.

Why?

Depending on the bitstream loaded to the FPGA, parts of the Flash
Memory or SRAM can hold configuration data which is non-volatile over
erase cycles. With this property, the board integrator, who knows about
the fpga design, can decide whether these areas shall be erased on
update or not. As an example, think of MAC addresses for a softcore
network interface stored in UFM (user flash memory), the board
integrator might want to decide to protect this memory area over
reflashing the fpga.

quoted

Signed-off-by: Johannes Zink <redacted>
---
 .../bindings/fpga/lattice,machxo2-slave.yaml      | 15
+++++++++++++++
 1 file changed, 15 insertions(+)

diff --git
a/Documentation/devicetree/bindings/fpga/lattice,machxo2-slave.yaml
b/Documentation/devicetree/bindings/fpga/lattice,machxo2-slave.yaml
index d05acd6b0fc6..78f0da8f772f 100644

--- a/Documentation/devicetree/bindings/fpga/lattice,machxo2-

slave.yaml

+++ b/Documentation/devicetree/bindings/fpga/lattice,machxo2-

slave.yaml

@@ -26,6 +26,19 @@ properties:

     enum:
       - lattice,machxo2-slave-spi
 
+  lattice,erase-sram:
+    type: boolean
+    description: SRAM is to be erased during flash erase operation
+
+  lattice,erase-feature-row:
+    type: boolean
+    description: Feature row is to be erased during flash erase
operation
+
+  lattice,erase-userflash:
+    type: boolean
+    description: |
+      UFM (user flash memory) is to be erased during flash erase
operation

These seem like policy. It this something that's really static to a 
particular board rather than something the user would configure each 
time.

From the usecases I can think of, for a given board with a given FPGA
design this is static. 

Best regards
Johannes

Rob

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