@@ -63,12 +63,12 @@ static const char *get_err_string(u8 err)
 	return "Unknown";
 }
 
-static void dump_status_reg(u32 status)
+static void dump_status_reg(struct device *dev, u32 status)
 {
-        pr_debug("machxo2 status: 0x%08X - done=%d, cfgena=%d, busy=%d, fail=%d, devver=%d, err=%s\n",
-                  status, !!FIELD_GET(MACHXO2_DONE, status), !!FIELD_GET(MACHXO2_ENAB, status),
-                  !!FIELD_GET(MACHXO2_BUSY, status), !!FIELD_GET(MACHXO2_FAIL, status),
-                  !!FIELD_GET(MACHXO2_DVER, status), get_err_string(get_err(status)));
+	dev_dbg(dev, "0x%08X - done=%d, cfgena=%d, busy=%d, fail=%d, devver=%d, err=%s\n",
+		status, !!FIELD_GET(MACHXO2_DONE, status), !!FIELD_GET(MACHXO2_ENAB, status),
+		!!FIELD_GET(MACHXO2_BUSY, status), !!FIELD_GET(MACHXO2_FAIL, status),
+		!!FIELD_GET(MACHXO2_DVER, status), get_err_string(get_err(status)));
 }
 
 static int machxo2_wait_until_not_busy(struct machxo2_common_priv *priv)

@@ -156,7 +156,7 @@ static int machxo2_write_init(struct fpga_manager *mgr,
 	}
 
 	priv->get_status(priv, &status);
-	dump_status_reg(status);
+	dump_status_reg(priv->dev, status);
 
 	cmd[0].cmd = enable;
 	cmd[0].cmd_len = sizeof(enable);

@@ -177,7 +177,7 @@ static int machxo2_write_init(struct fpga_manager *mgr,
 		ret = -EINVAL;
 		goto fail;
 	}
-	dump_status_reg(status);
+	dump_status_reg(priv->dev, status);
 
 	cmd[0].cmd = initaddr;
 	cmd[0].cmd_len = sizeof(initaddr);

@@ -186,7 +186,7 @@ static int machxo2_write_init(struct fpga_manager *mgr,
 		goto fail;
 
 	priv->get_status(priv, &status);
-	dump_status_reg(status);
+	dump_status_reg(priv->dev, status);
 
 	return 0;
 fail:

@@ -210,7 +210,7 @@ static int machxo2_write(struct fpga_manager *mgr, const char *buf,
 		return -EINVAL;
 	}
 	priv->get_status(priv, &status);
-	dump_status_reg(status);
+	dump_status_reg(priv->dev, status);
 	cmd.cmd = payload;
 	cmd.cmd_len = MACHXO2_BUF_SIZE;
 	cmd.delay_us = MACHXO2_HIGH_DELAY_USEC;

@@ -229,7 +229,7 @@ static int machxo2_write(struct fpga_manager *mgr, const char *buf,
 		}
 	}
 	priv->get_status(priv, &status);
-	dump_status_reg(status);
+	dump_status_reg(priv->dev, status);
 
 	return 0;
 }

@@ -254,7 +254,7 @@ static int machxo2_write_complete(struct fpga_manager *mgr,
 		goto fail;
 
 	priv->get_status(priv, &status);
-	dump_status_reg(status);
+	dump_status_reg(priv->dev, status);
 	if (!(status & MACHXO2_DONE)) {
 		machxo2_cleanup(mgr);
 		ret = -EINVAL;

@@ -272,7 +272,7 @@ static int machxo2_write_complete(struct fpga_manager *mgr,
 
 		/* check refresh status */
 		priv->get_status(priv, &status);
-		dump_status_reg(status);
+		dump_status_reg(priv->dev, status);
 		if (machxo2_status_done(status))
 			break;
 		if (++refreshloop == MACHXO2_MAX_REFRESH_LOOP) {

@@ -283,7 +283,7 @@ static int machxo2_write_complete(struct fpga_manager *mgr,
 	} while (1);
 
 	priv->get_status(priv, &status);
-	dump_status_reg(status);
+	dump_status_reg(priv->dev, status);
 
 	return 0;
 fail:

@@ -303,6 +303,8 @@ int machxo2_common_init(struct machxo2_common_priv *priv, struct device *dev)
 {
 	struct fpga_manager *mgr;
 
+	priv->dev = dev;
+
 	mgr = devm_fpga_mgr_register(dev, "Lattice MachXO2 SPI FPGA Manager",
 				     &machxo2_ops, priv);
 

@@ -30,6 +30,7 @@ struct machxo2_common_priv {
 	int (*write_commands)(struct machxo2_common_priv *priv,
 			     struct machxo2_cmd *cmds, size_t cmd_count);
 	int (*get_status)(struct machxo2_common_priv *priv, u32 *status);
+	struct device *dev;
 };
 
 int machxo2_common_init(struct machxo2_common_priv *priv, struct device *dev);