On Tue, 9 Nov 2021 at 01:46, Linus Walleij [off-list ref] wrote:

On Tue, Nov 2, 2021 at 5:12 PM Emil Renner Berthing [off-list ref] wrote:

quoted

Add bindings for the GPIO/pin controller on the JH7100 RISC-V SoC by
StarFive Ltd. This is a test chip for their upcoming JH7110 SoC.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---

@Linus: I'm really struggling to find a good way to describe how pin
muxing works on the JH7100. As you can see I've now resorted to
ascii-art to try to explain it, but please let me know if it's still
unclear.

This looks perfectly acceptable to me:
Reviewed-by: Linus Walleij <redacted>

Thank you.

As it appears to have some cross dependencies I assume
it will be merged through the SoC tree?

I don't know. I've never tried this before, so whatever is easiest I
guess. Do I do anything special other than cc'ing soc@kernel.org for
v4 to make that happen?

/Emil