[RFC 5/5] arm64: dts: imx8mm: Enable Hantro H1 Encoder
From: Adam Ford <hidden>
Date: 2021-11-06 18:38:49
Also in:
linux-arm-kernel, linux-media, linux-rockchip, linux-staging, lkml
Subsystem:
arm/freescale imx / mxc arm architecture, the rest · Maintainers:
Frank Li, Sascha Hauer, Linus Torvalds
The i.MX8M Mini has a Hantro H1 video encoder which appears
as a media device.
Media device information
------------------------
driver hantro-vpu
model hantro-vpu
serial
bus info platform: hantro-vpu
hw revision 0x0
driver version 5.15.0
Device topology
- entity 1: nxp,imx8mm-vpu-h1-enc-source (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video3
pad0: Source
-> "nxp,imx8mm-vpu-h1-enc-proc":0 [ENABLED,IMMUTABLE]
- entity 3: nxp,imx8mm-vpu-h1-enc-proc (2 pads, 2 links)
type Node subtype Unknown flags 0
pad0: Sink
<- "nxp,imx8mm-vpu-h1-enc-source":0 [ENABLED,IMMUTABLE]
pad1: Source
-> "nxp,imx8mm-vpu-h1-enc-sink":0 [ENABLED,IMMUTABLE]
- entity 6: nxp,imx8mm-vpu-h1-enc-sink (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video3
pad0: Sink
<- "nxp,imx8mm-vpu-h1-enc-proc":1 [ENABLED,IMMUTABLE]
Signed-off-by: Adam Ford <redacted>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 725c3113831e..b4c204cbced8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi@@ -1289,6 +1289,26 @@ vpu_g2: video-codec@38310000 { power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>; }; + vpu_h1: video-codec@38320000 { + compatible = "nxp,imx8mm-vpu-h1"; + reg = <0x38320000 0x10000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "h1"; + clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>, + <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + clock-names = "h1", "bus"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_H1>, + <&clk IMX8MM_CLK_VPU_BUS>, + <&clk IMX8MM_VPU_PLL_BYPASS>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, + <&clk IMX8MM_SYS_PLL1_800M>, + <&clk IMX8MM_VPU_PLL>; + assigned-clock-rates = <600000000>, + <800000000>, + <0>; + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_H1>; + }; + vpu_blk_ctrl: blk-ctrl@38330000 { compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; reg = <0x38330000 0x100>;
--
2.32.0