Re: [PATCH v2 4/5] ASoC: codecs: tx-macro: Update tx default values
From: Srinivas Kandagatla <hidden>
Date: 2021-09-27 10:42:59
Also in:
alsa-devel, linux-arm-msm, lkml
Possibly related (same subject, not in this thread)
- 2021-10-08 · Re: [PATCH v2 4/5] ASoC: codecs: tx-macro: Update tx default values · Mark Brown <broonie@kernel.org>
- 2021-10-08 · Re: [PATCH v2 4/5] ASoC: codecs: tx-macro: Update tx default values · Srinivasa Rao Mandadapu <hidden>
- 2021-09-28 · Re: [PATCH v2 4/5] ASoC: codecs: tx-macro: Update tx default values · Srinivas Kandagatla <hidden>
On 22/09/2021 13:31, Srinivasa Rao Mandadapu wrote:
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Update mic control register default values to hardware reset values Fixes: c39667ddcfc5 (ASoC: codecs: lpass-tx-macro: add support for lpass tx macro) Signed-off-by: Venkata Prasad Potturu <redacted> Signed-off-by: Srinivasa Rao Mandadapu <redacted> --- sound/soc/codecs/lpass-tx-macro.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)diff --git a/sound/soc/codecs/lpass-tx-macro.c b/sound/soc/codecs/lpass-tx-macro.c index e980b2e..66c39fb 100644 --- a/sound/soc/codecs/lpass-tx-macro.c +++ b/sound/soc/codecs/lpass-tx-macro.c@@ -279,7 +279,7 @@ static const struct reg_default tx_defaults[] = { { CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00}, { CDC_TX_TOP_CSR_TOP_CFG0, 0x00}, { CDC_TX_TOP_CSR_ANC_CFG, 0x00}, - { CDC_TX_TOP_CSR_SWR_CTRL, 0x00}, + { CDC_TX_TOP_CSR_SWR_CTRL, 0x60},
This does not make sense as this register only has one bit to control. Why do we even need to change this, can you please explain what happens if we do not change this?
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{ CDC_TX_TOP_CSR_FREQ_MCLK, 0x00}, { CDC_TX_TOP_CSR_DEBUG_BUS, 0x00}, { CDC_TX_TOP_CSR_DEBUG_EN, 0x00},@@ -290,8 +290,8 @@ static const struct reg_default tx_defaults[] = { { CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00}, { CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00}, { CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00}, - { CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00}, - { CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00}, + { CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x0E}, + { CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x0E},
These two registers should have default value of 0x06 as this has only one clk selection field with bits 2:1. -srini
{ CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00},
{ CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00},
{ CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00},