On 9/28/2021 2:01 PM, Srinivas Kandagatla wrote:

On 27/09/2021 17:42, Srinivasa Rao Mandadapu wrote:

quoted

On 9/27/2021 4:12 PM, Srinivas Kandagatla wrote:
Thanks for your time Srini!!

quoted

On 22/09/2021 13:31, Srinivasa Rao Mandadapu wrote:

quoted

Update mic control register default values to hardware reset values

Fixes: c39667ddcfc5 (ASoC: codecs: lpass-tx-macro: add support for 
lpass tx macro)

Signed-off-by: Venkata Prasad Potturu <redacted>
Signed-off-by: Srinivasa Rao Mandadapu <redacted>
---
  sound/soc/codecs/lpass-tx-macro.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/sound/soc/codecs/lpass-tx-macro.c 

b/sound/soc/codecs/lpass-tx-macro.c
index e980b2e..66c39fb 100644

--- a/sound/soc/codecs/lpass-tx-macro.c
+++ b/sound/soc/codecs/lpass-tx-macro.c

@@ -279,7 +279,7 @@ static const struct reg_default tx_defaults[] = {

      { CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00},
      { CDC_TX_TOP_CSR_TOP_CFG0, 0x00},
      { CDC_TX_TOP_CSR_ANC_CFG, 0x00},
-    { CDC_TX_TOP_CSR_SWR_CTRL, 0x00},
+    { CDC_TX_TOP_CSR_SWR_CTRL, 0x60},

This does not make sense as this register only has one bit to control.
Why do we even need to change this, can you please explain what 
happens if we do not change this?

This register change is not making any impact. But when verified , 
reset state of this register is 0x60. so is the reason for change.

Will revert it and post again.

quoted

quoted

      { CDC_TX_TOP_CSR_FREQ_MCLK, 0x00},
      { CDC_TX_TOP_CSR_DEBUG_BUS, 0x00},
      { CDC_TX_TOP_CSR_DEBUG_EN, 0x00},

@@ -290,8 +290,8 @@ static const struct reg_default tx_defaults[] = {

      { CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00},
      { CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00},
      { CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00},
-    { CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00},
-    { CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00},
+    { CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x0E},
+    { CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x0E},

These two registers should have default value of 0x06 as this has 
only one clk selection field with bits 2:1.

In Kodiak document reset state 0x0E and clk selection field is with 
bits 3:1

*LPASS_TX_TX_TOP_CSR_SWR_MIC1_CTL*|0x32200D4
Offset:     0x54     Reset State:     0x0000000E 

In that case you should probably consider using 
regmap_register_patch() for corrections to the default registers in 
sm8250 case.

As regmap_register_patch() not working in this use case, updating 
defaults in probe for sc7280 specific differences.

--srini

quoted

quoted

-srini

quoted

      { CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00},
      { CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00},
      { CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00},

-- 
Qualcomm India Private Limited, on behalf of Qualcomm Innovation 
Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative 
Project.

-- 
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.