Thread (15 messages) 15 messages, 3 authors, 2021-08-25

RE: [PATCH v2 1/9] dt-bindings: clock: Add imx8ulp clock support

From: Jacky Bai <ping.bai@nxp.com>
Date: 2021-08-23 05:43:35

Subject: Re: [PATCH v2 1/9] dt-bindings: clock: Add imx8ulp clock support

On Tue, Aug 10, 2021 at 02:28:12PM +0800, Jacky Bai wrote:
quoted
Add the clock dt-binding file for i.MX8ULP.

For pcc node, it will also be used as a reset controller, so add the
'#reset-cells' property description and add the pcc reset IDs.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
---
 v2 changes:
   - removed the redundant clocks & clock-names property

 v1 changes:
   - Move this patch from dts patchset into this patchset
---
 .../bindings/clock/imx8ulp-clock.yaml         |  71 +++++
 include/dt-bindings/clock/imx8ulp-clock.h     | 258 ++++++++++++++++++
 include/dt-bindings/reset/imx8ulp-pcc-reset.h |  59 ++++
 3 files changed, 388 insertions(+)
 create mode 100644
Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
 create mode 100644 include/dt-bindings/clock/imx8ulp-clock.h
 create mode 100644 include/dt-bindings/reset/imx8ulp-pcc-reset.h

diff --git
a/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
b/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
new file mode 100644
index 000000000000..9a075de1086a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
+---
...
quoted
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - fsl,imx8ulp-pcc3
+              - fsl,imx8ulp-pcc4
+              - fsl,imx8ulp-pcc5
+    then:
+      required:
+        - '#reset-cells'
And #reset-cells is optional for a CGC? I think this should be 2 schema files.
There's nothing really shared any more than any other clock/reset controller.
The CGC is a root clock generator, has no reset function, only the PCC HW modules have reset control for peripherals.
Do you suggest to spit into two schema files, one for CGCs, and another one for PCCs?
Thanks.

BR
quoted
+
+additionalProperties: false
+
+examples:
+  # Clock Control Module node:
+  - |
+    clock-controller@292c0000 {
+        compatible = "fsl,imx8ulp-cgc1";
+        reg = <0x292c0000 0x10000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    clock-controller@292d0000 {
+        compatible = "fsl,imx8ulp-pcc3";
+        reg = <0x292d0000 0x10000>;
+        #clock-cells = <1>;
+        #reset-cells = <1>;
+    };
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