Re: [PATCH v2 1/9] dt-bindings: clock: Add imx8ulp clock support
From: Rob Herring <robh@kernel.org>
Date: 2021-08-17 19:15:21
On Tue, Aug 10, 2021 at 02:28:12PM +0800, Jacky Bai wrote:
quoted hunk ↗ jump to hunk
Add the clock dt-binding file for i.MX8ULP. For pcc node, it will also be used as a reset controller, so add the '#reset-cells' property description and add the pcc reset IDs. Signed-off-by: Jacky Bai <ping.bai@nxp.com> --- v2 changes: - removed the redundant clocks & clock-names property v1 changes: - Move this patch from dts patchset into this patchset --- .../bindings/clock/imx8ulp-clock.yaml | 71 +++++ include/dt-bindings/clock/imx8ulp-clock.h | 258 ++++++++++++++++++ include/dt-bindings/reset/imx8ulp-pcc-reset.h | 59 ++++ 3 files changed, 388 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml create mode 100644 include/dt-bindings/clock/imx8ulp-clock.h create mode 100644 include/dt-bindings/reset/imx8ulp-pcc-reset.hdiff --git a/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml b/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml new file mode 100644 index 000000000000..9a075de1086a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml@@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx8ulp-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8ULP Clock Control Module Binding + +maintainers: + - Jacky Bai <ping.bai@nxp.com> + +description: | + On i.MX8ULP, The clock sources generation, distribution and management is + under the control of several CGCs & PCCs modules. The CGC modules generate + and distribute clocks on the device. PCC modules control software reset, + clock selection, optional division and clock gating mode for peripherals. + +properties: + compatible: + enum: + - fsl,imx8ulp-cgc1 + - fsl,imx8ulp-cgc2 + - fsl,imx8ulp-pcc3 + - fsl,imx8ulp-pcc4 + - fsl,imx8ulp-pcc5 + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8ulp-pcc3 + - fsl,imx8ulp-pcc4 + - fsl,imx8ulp-pcc5 + then: + required: + - '#reset-cells'
And #reset-cells is optional for a CGC? I think this should be 2 schema files. There's nothing really shared any more than any other clock/reset controller.
+
+additionalProperties: false
+
+examples:
+ # Clock Control Module node:
+ - |
+ clock-controller@292c0000 {
+ compatible = "fsl,imx8ulp-cgc1";
+ reg = <0x292c0000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ - |
+ clock-controller@292d0000 {
+ compatible = "fsl,imx8ulp-pcc3";
+ reg = <0x292d0000 0x10000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };