RE: [PATCH v2] dt-bindings: net: renesas,etheravb: Document Gigabit Ethernet IP

Hi Geert,

Thanks for the feedback.

Subject: Re: [PATCH v2] dt-bindings: net: renesas,etheravb: Document
Gigabit Ethernet IP

Hi Biju,

On Tue, Jul 27, 2021 at 2:35 PM Biju Das [off-list ref]
wrote:

quoted

Document Gigabit Ethernet IP found on RZ/G2L SoC.

Gigabit Ethernet Interface includes Ethernet controller (E-MAC),
Internal TCP/IP Offload Engine (TOE) and Dedicated Direct memory
access controller (DMAC) for transferring transmitted Ethernet frames
to and received Ethernet frames from respective storage areas in the
URAM at high speed.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

quoted

--- a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
+++ b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml

quoted

@@ -145,14 +142,20 @@ allOf:
       properties:
         compatible:
           contains:
-            const: renesas,etheravb-rcar-gen2
+            enum:
+              - renesas,etheravb-rcar-gen2
+              - renesas,rzg2l-gbeth
     then:
       properties:
         interrupts:
-          maxItems: 1
+          minItems: 1
+          maxItems: 3
         interrupt-names:
+          minItems: 1
           items:
             - const: mux
+            - const: int_fil_n
+            - const: int_arp_ns_n

I'm aware Rob has already applied this, but should the "int_" prefix be
dropped?

OK. I will use "fil" and "arp" instead.

The "_n" suffix is also a bit weird (albeit it matches the documentation).
Usually it is used to indicate an active-low signal, but the interrupt is
declared in the .dtsi with IRQ_TYPE_LEVEL_HIGH.

But here on the interrupt mapping table(RZG2L_InterruptMapping_rev01.xlsx). It is mentioned as high. So I guess, it is correct.

And the first interrupt is not a mux on RZ/G2L, but called "pif_int_n"
(whatever "pif" might mean).

As per section 32.5.12 Interrupts, this interrupt include, Descriptor interrupts,
Error interrupts, reception interrupts and transmission interrupts.

The source status can be checked from individual status register. 

For me. This description looks like a mux interrupt.
Multiple interrupt sources ored together to generate an interrupt and status can be 
Checked from each individual register. 
Please let me know if my understanding is wrong.

I agree, on HW manual it is mentioned as pif_int_n. I can replace mux with pif instead. Please let me know.

Regards,
Biju

quoted

         rx-internal-delay-ps: false
     else:
       properties:

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
m68k.org

In personal conversations with technical people, I call myself a hacker.
But when I'm talking to journalists I just say "programmer" or something
like that.
                                -- Linus Torvalds