On Wed, 2021-07-21 at 21:40 +0800, Ikjoon Jang wrote:

On Thu, Jul 15, 2021 at 8:23 PM Yong Wu [off-list ref] wrote:

quoted

To improve the performance, We add some initial setting for smi larbs.
there are two part:
1), Each port has the special ostd(outstanding) value in each larb.
2), Two general setting for each larb.

In some SoC, this setting maybe changed dynamically for some special case
like 4K, and this initial setting is enough in mt8195.

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---

[...]

quoted

 struct mtk_smi {

@@ -213,12 +228,22 @@ static void mtk_smi_larb_config_port_mt8173(struct device *dev)
 static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
 {
        struct mtk_smi_larb *larb = dev_get_drvdata(dev);
-       u32 reg;
+       u32 reg, flags_general = larb->larb_gen->flags_general;
+       const u8 *larbostd = larb->larb_gen->ostd[larb->larbid];
        int i;

        if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
                return;

+       if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_LARB_THRT_EN))
+               writel_relaxed(SMI_LARB_THRT_EN, larb->base + SMI_LARB_CMD_THRT_CON);
+
+       if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_LARB_SW_FLAG))
+               writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG);
+
+       for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++)
+               writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i));

All other mtk platform's larbs have the same format for SMI_LARB_OSTDL_PORTx()
registers at the same offset? or is this unique feature for mt8195?

All the other Platform's larbs have the same format at the same offset.

quoted

+
        for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
                reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
                reg |= F_MMU_EN;

@@ -227,6 +252,51 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
        }
 }

[...]