To improve the performance, add initial setting for smi-common.
some register use some fix setting(suggested from DE).

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
 drivers/memory/mtk-smi.c | 42 ++++++++++++++++++++++++++++++++++++----
 1 file changed, 38 insertions(+), 4 deletions(-)

diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 3c288716a378..c52bf02458ff 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c

@@ -18,11 +18,19 @@
 #include <dt-bindings/memory/mtk-memory-port.h>

 /* SMI COMMON */
+#define SMI_L1LEN                      0x100
+
 #define SMI_BUS_SEL                    0x220
 #define SMI_BUS_LARB_SHIFT(larbid)     ((larbid) << 1)
 /* All are MMU0 defaultly. Only specialize mmu1 here. */
 #define F_MMU1_LARB(larbid)            (0x1 << SMI_BUS_LARB_SHIFT(larbid))

+#define SMI_M4U_TH                     0x234
+#define SMI_FIFO_TH1                   0x238
+#define SMI_FIFO_TH2                   0x23c
+#define SMI_DCM                                0x300
+#define SMI_DUMMY                      0x444
+
 /* SMI LARB */

 /* Below are about mmu enable registers, they are different in SoCs */

@@ -58,6 +66,13 @@
        (_id << 8 | _id << 10 | _id << 12 | _id << 14); \
 })

+#define SMI_COMMON_INIT_REGS_NR                6
+
+struct mtk_smi_reg_pair {
+       unsigned int            offset;
+       u32                     value;
+};
+
 enum mtk_smi_type {
        MTK_SMI_GEN1,
        MTK_SMI_GEN2,           /* gen2 smi common */

@@ -74,6 +89,8 @@ static const char * const mtk_smi_larb_clks_optional[] = {"gals"};
 struct mtk_smi_common_plat {
        enum mtk_smi_type       type;
        u32                     bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
+
+       const struct mtk_smi_reg_pair   *init;
 };

 struct mtk_smi_larb_gen {

@@ -409,6 +426,15 @@ static struct platform_driver mtk_smi_larb_driver = {
        }
 };

+static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = {
+       {SMI_L1LEN, 0xb},
+       {SMI_M4U_TH, 0xe100e10},
+       {SMI_FIFO_TH1, 0x506090a},
+       {SMI_FIFO_TH2, 0x506090a},
+       {SMI_DCM, 0x4f1},
+       {SMI_DUMMY, 0x1},
+};
+
 static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
        .type     = MTK_SMI_GEN1,
 };

@@ -439,11 +465,13 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = {
        .type     = MTK_SMI_GEN2,
        .bus_sel  = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) |
                    F_MMU1_LARB(7),
+       .init     = mtk_smi_common_mt8195_init,
 };

 static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = {
        .type     = MTK_SMI_GEN2,
        .bus_sel  = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7),
+       .init     = mtk_smi_common_mt8195_init,
 };

 static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = {

@@ -530,15 +558,21 @@ static int mtk_smi_common_remove(struct platform_device *pdev)
 static int __maybe_unused mtk_smi_common_resume(struct device *dev)
 {
        struct mtk_smi *common = dev_get_drvdata(dev);
-       u32 bus_sel = common->plat->bus_sel;
-       int ret;
+       const struct mtk_smi_reg_pair *init = common->plat->init;
+       u32 bus_sel = common->plat->bus_sel; /* default is 0 */
+       int ret, i;

        ret = clk_bulk_prepare_enable(common->clk_num, common->clks);
        if (ret)
                return ret;

-       if (common->plat->type == MTK_SMI_GEN2 && bus_sel)
-               writel(bus_sel, common->base + SMI_BUS_SEL);
+       if (common->plat->type != MTK_SMI_GEN2)
+               return 0;
+
+       for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++)
+               writel_relaxed(init[i].value, common->base + init[i].offset);