[PATCH v4 4/5] MIPS: CI20: Reduce clocksource to 750 kHz.
From: 周琰杰 (Zhou Yanjie) <hidden>
Date: 2021-06-26 06:19:06
Also in:
linux-clk, linux-mips, lkml
Subsystem:
ingenic jz47xx socs, mips, the rest · Maintainers:
Paul Cercueil, Thomas Bogendoerfer, Linus Torvalds
The original clock (3 MHz) is too fast for the clocksource,
there will be a chance that the system may get stuck.
Reported-by: Nikolaus Schaller <redacted>
Tested-by: Nikolaus Schaller <redacted> # on CI20
Signed-off-by: 周琰杰 (Zhou Yanjie) <redacted>
---
Notes:
v4:
New patch.
arch/mips/boot/dts/ingenic/ci20.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 8877c62..3a4eaf1 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts@@ -525,10 +525,10 @@ &tcu { /* - * 750 kHz for the system timer and 3 MHz for the clocksource, + * 750 kHz for the system timer and clocksource, * use channel #0 for the system timer, #1 for the clocksource. */ assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, <&tcu TCU_CLK_OST>; - assigned-clock-rates = <750000>, <3000000>, <3000000>; + assigned-clock-rates = <750000>, <750000>, <3000000>; };
--
2.7.4