If N fields of X cells should be provided, then that's what the
devicetree should represent, instead of having one single field of
(N * X) cells.
Signed-off-by: 周琰杰 (Zhou Yanjie) <redacted>
Acked-by: Paul Cercueil <paul@crapouillou.net>
---
Notes:
v1->v2:
No change.
v2->v3:
No change.
v3->v4:
No change.
arch/mips/boot/dts/ingenic/x1830.dtsi | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
Hi Stephen,
于 Sun, 27 Jun 2021 19:52:02 -0700
Stephen Boyd [off-list ref] 写道:
Quoting 周琰杰 (Zhou Yanjie) (2021-06-25 23:18:38)
quoted
Update the CGU binding documentation, add mac-phy-ctrl as a
pattern property.
Signed-off-by: 周琰杰 (Zhou Yanjie) <redacted>
Acked-by: Paul Cercueil <paul@crapouillou.net>
---
Acked-by: Stephen Boyd <sboyd@kernel.org>
Thanks!
Would also be good to add it to the example.
Unfortunately, mac-phy-ctrl only appeared after JZ4775 (include JZ4775),
but now the CGU driver of JZ4775 has not been merged into the mainline.
My plan is to wait for the CGU driver of JZ4775 to be merged into the
mainline and then add a new example based on JZ4775 :)
Thanks and best regards!
1.Add a new TCU channel as the percpu timer of core1, this is to
prepare for the subsequent SMP support. The newly added channel
will not adversely affect the current single-core state.
2.Adjust the position of TCU node to make it consistent with the
order in jz4780.dtsi file.
Tested-by: Nikolaus Schaller <redacted> # on CI20
Signed-off-by: 周琰杰 (Zhou Yanjie) <redacted>
---
Notes:
v2:
New patch.
v2->v3:
No change.
v3->v4:
Improve TCU related notes.
arch/mips/boot/dts/ingenic/ci20.dts | 24 ++++++++++++++----------
1 file changed, 14 insertions(+), 10 deletions(-)
From: Paul Cercueil <paul@crapouillou.net> Date: 2021-06-30 12:24:23
Hi Zhou,
Le sam., juin 26 2021 at 14:18:41 +0800, 周琰杰 (Zhou Yanjie)
[off-list ref] a écrit :
1.Add a new TCU channel as the percpu timer of core1, this is to
prepare for the subsequent SMP support. The newly added channel
will not adversely affect the current single-core state.
2.Adjust the position of TCU node to make it consistent with the
order in jz4780.dtsi file.
Tested-by: Nikolaus Schaller <redacted> # on CI20
Signed-off-by: 周琰杰 (Zhou Yanjie) <redacted>
Again, you should avoid moving nodes like that.
Not sure it's worth asking for a v5, so:
Acked-by: Paul Cercueil <paul@crapouillou.net>
Cheers,
-Paul
quoted hunk
---
Notes:
v2:
New patch.
v2->v3:
No change.
v3->v4:
Improve TCU related notes.
arch/mips/boot/dts/ingenic/ci20.dts | 24 ++++++++++++++----------
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
b/arch/mips/boot/dts/ingenic/ci20.dts
index 3a4eaf1..61c153b 100644
Hi Zhou,
Le sam., juin 26 2021 at 14:18:41 +0800, 周琰杰 (Zhou Yanjie)
[off-list ref] a écrit :
quoted
1.Add a new TCU channel as the percpu timer of core1, this is to
prepare for the subsequent SMP support. The newly added channel
will not adversely affect the current single-core state.
2.Adjust the position of TCU node to make it consistent with the
order in jz4780.dtsi file.
Tested-by: Nikolaus Schaller <redacted> # on CI20
Signed-off-by: 周琰杰 (Zhou Yanjie) <redacted>
Again, you should avoid moving nodes like that.
Oops, sorry, forgot to fix it, I will be more careful next time.
Not sure it's worth asking for a v5, so:
Acked-by: Paul Cercueil <paul@crapouillou.net>
Thanks!
Cheers,
-Paul
quoted
---
Notes:
v2:
New patch.
v2->v3:
No change.
v3->v4:
Improve TCU related notes.
arch/mips/boot/dts/ingenic/ci20.dts | 24 ++++++++++++++----------
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
b/arch/mips/boot/dts/ingenic/ci20.dts
index 3a4eaf1..61c153b 100644
assigned-clock-rates = <48000000>;
};
+&tcu {
+ /*
+ * 750 kHz for the system timers and clocksource,
+ * use channel #0 and #1 for the per cpu system timers,
+ * and use channel #2 for the clocksource.
+ *
+ * 3000 kHz for the OST timer to provide a higher
+ * precision clocksource.
+ */
+ assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
+ <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>;
+ assigned-clock-rates = <750000>, <750000>, <750000>, <3000000>;
+};
+
&mmc0 {
status = "okay";
@@ -522,13 +536,3 @@
bias-disable;
};
};
-
-&tcu {
- /*
- * 750 kHz for the system timer and clocksource,
- * use channel #0 for the system timer, #1 for the clocksource.
- */
- assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
- <&tcu TCU_CLK_OST>;
- assigned-clock-rates = <750000>, <750000>, <3000000>;
-};
--
2.7.4
The original clock (3 MHz) is too fast for the clocksource,
there will be a chance that the system may get stuck.
Reported-by: Nikolaus Schaller <redacted>
Tested-by: Nikolaus Schaller <redacted> # on CI20
Signed-off-by: 周琰杰 (Zhou Yanjie) <redacted>
---
Notes:
v4:
New patch.
arch/mips/boot/dts/ingenic/ci20.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
From: Paul Cercueil <paul@crapouillou.net> Date: 2021-06-30 12:21:30
Hi Zhou,
Le sam., juin 26 2021 at 14:18:40 +0800, 周琰杰 (Zhou Yanjie)
[off-list ref] a écrit :
The original clock (3 MHz) is too fast for the clocksource,
there will be a chance that the system may get stuck.
Reported-by: Nikolaus Schaller <redacted>
Tested-by: Nikolaus Schaller <redacted> # on CI20
Signed-off-by: 周琰杰 (Zhou Yanjie) <redacted>
Acked-by: Paul Cercueil <paul@crapouillou.net>
Cheers,
-Paul