Re: [PATCH v2] arm64/dts/qcom/sc7180: Add Display Port dt node

Quoting khsieh@codeaurora.org (2021-06-10 09:54:05)

On 2021-06-08 16:10, Bjorn Andersson wrote:

quoted

On Tue 08 Jun 17:44 CDT 2021, Stephen Boyd wrote:

quoted

Honestly I suspect the DP PHY is _not_ in the CX domain as CX is for
digital logic. Probably the PLL is the hardware that has some minimum
CX
requirement, and that flows down into the various display clks like
the
link clk that actually clock the DP controller hardware. The mdss_gdsc
probably gates CX for the display subsystem (mdss) so if we had proper
corner aggregation logic we could indicate that mdss_gdsc is a child
of
the CX domain and then make requests from the DP driver for particular
link frequencies on the mdss_gdsc and then have that bubble up to CX
appropriately. I don't think any of that sort of code is in place
though, right?

I haven't checked sc7180, but I'm guessing that it's following the
other
modern platforms, where all the MDSS related pieces (including e.g.
dispcc) lives in the MMCX domain, which is separate from CX.

So the parent of MDSS_GDSC should be MMCX, while Kuogee's answer (and
the dp-opp-table) tells us that the PLL lives in the CX domain.

Isn't MMCX a "child" of CX? At least my understanding is that MMCX is
basically a GDSC that clamps all of multimedia hardware block power
logic so that the leakage is minimized when multimedia isn't in use,
i.e. the device is suspended. In terms of bumping up the voltage we have
to pin that on CX though as far as I know because that's the only power
domain that can actually change voltage, while MMCX merely gates that
voltage for multimedia.

quoted

PS. While this goes for the QMPs the DSI and eDP/DP PHYs (and PLLs)
seems to live in MMCX.

Regards,
Bjorn

Dp link clock rate is sourced from phy/pll (vco). However it is possible
that different link clock rate
are sourced from same vco (phy/pll) rate. Therefore I think CX rail
voltage level is more proper to
be decided base on link clock rate.