Hi Prabhakar,

On Fri, May 21, 2021 at 6:54 PM Lad, Prabhakar
[off-list ref] wrote:

On Fri, May 21, 2021 at 2:23 PM Geert Uytterhoeven [off-list ref] wrote:

quoted

On Fri, May 14, 2021 at 9:23 PM Lad Prabhakar
[off-list ref] wrote:

quoted

Add device tree bindings documentation for Renesas RZ/G2UL SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Chris Paterson <redacted>

Thanks for your patch!

quoted

--- a/Documentation/devicetree/bindings/arm/renesas.yaml
+++ b/Documentation/devicetree/bindings/arm/renesas.yaml

@@ -302,6 +302,12 @@ properties:
               - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
           - const: renesas,r9a06g032

+      - description: RZ/G2UL (R9A07G043)
+        items:
+          - enum:
+              - renesas,r9a07g043u11 # Single Cortex-A55 RZ/G2UL

Is there any specific reason you're including the final "1", unlike the
RZ/G2{L,LC} binding?

To be consistent with the RZ/G2L family of SoC's "1" is appended to
the compatible string.

No, for RZ/G2L you have:

    renesas,r9a07g044c1 for r9a07g044c12
    renesas,r9a07g044c2 for r9a07g044c22
    renesas,r9a07g044l1 for r9a07g044l13 and r9a07g044l14
    renesas,r9a07g044l2 for r9a07g044l23 and r9a07g044l24

i.e. the compatible value lacks the final digit.

For RZ/G2UL, I do not know if we have to distinguish between
r9a07g043u11 and r9a07g043u12.

quoted

As RZ/G2UL is always single-core, perhaps this compatible value can be
dropped?

Do agree with you.

In light of the continued discussion for [PATCH 02/16], perhaps it's
good to keep it anyway?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds